TI DS92LV18TVVX/NOPB
| Manufacturer | |
| MPN | DS92LV18TVVX/NOPB |
| LCSC Part # | C544419 |
| Packaging | LQFP-80(12x12) |
| Customer # | |
| Key Attributes | DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66MHz |
| Datasheet |  TI DS92LV18TVVX/NOPB |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Serializers, Deserializers | |
| Manufacturer | TI | |
| Packaging | LQFP-80(12x12) | |
| Output | - | |
| Clock Frequency | 66MHz | |
| Input | LVCMOS;LVTTL | |
| Data Rate | 2.376Gbps | |
| Number of ports | 1 | |
| Type | Serializer, Deserializer | |
| Voltage - Supply | 3.15V~3.45V | |
| Parallel Bit Count Per Channel | 18 | |
| Features | Built-in phase-locked loop;Link status monitoring | |
| Operating Temperature | -40℃~+85℃ | |
| Control Interface | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Serializers, Deserializers | |
| Manufacturer | TI | |
| Packaging | LQFP-80(12x12) | |
| Output | - | |
| Clock Frequency | 66MHz | |
| Input | LVCMOS;LVTTL | |
| Data Rate | 2.376Gbps |
| Type | Description | |
|---|---|---|
| Number of ports | 1 | |
| Type | Serializer, Deserializer | |
| Voltage - Supply | 3.15V~3.45V | |
| Parallel Bit Count Per Channel | 18 | |
| Features | Built-in phase-locked loop;Link status monitoring | |
| Operating Temperature | -40℃~+85℃ | |
| Control Interface | - |
Introduction
The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side. The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.
Features
- 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput)
- Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins
- Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data)
- Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
- Line and Local Loopback Modes
- Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
- No External Coding Required
- Internal PLL, No External PLL Components Required
- Single +3.3V Power Supply
- Low Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern
- ±100 mv Receiver Input Threshold
- Loss of Lock Detection and Reporting Pin
- Industrial -40 to +85°C Temperature Range
-
2.0 KV HBM ESD
- Compact, Standard 80-Pin LQFP Package
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 18.7422 | $ 18.74 |
| 30+ | $ 18.0843 | $ 542.53 |
Standard Packaging1000/Full Reel | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Serializers, Deserializers | |
| Manufacturer | TI | |
| Packaging | LQFP-80(12x12) | |
| Output | - | |
| Clock Frequency | 66MHz | |
| Input | LVCMOS;LVTTL | |
| Data Rate | 2.376Gbps | |
| Number of ports | 1 | |
| Type | Serializer, Deserializer | |
| Voltage - Supply | 3.15V~3.45V | |
| Parallel Bit Count Per Channel | 18 | |
| Features | Built-in phase-locked loop;Link status monitoring | |
| Operating Temperature | -40℃~+85℃ | |
| Control Interface | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Serializers, Deserializers | |
| Manufacturer | TI | |
| Packaging | LQFP-80(12x12) | |
| Output | - | |
| Clock Frequency | 66MHz | |
| Input | LVCMOS;LVTTL | |
| Data Rate | 2.376Gbps |
| Type | Description | |
|---|---|---|
| Number of ports | 1 | |
| Type | Serializer, Deserializer | |
| Voltage - Supply | 3.15V~3.45V | |
| Parallel Bit Count Per Channel | 18 | |
| Features | Built-in phase-locked loop;Link status monitoring | |
| Operating Temperature | -40℃~+85℃ | |
| Control Interface | - |
Introduction
The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side. The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.
Features
- 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput)
- Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins
- Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data)
- Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
- Line and Local Loopback Modes
- Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
- No External Coding Required
- Internal PLL, No External PLL Components Required
- Single +3.3V Power Supply
- Low Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern
- ±100 mv Receiver Input Threshold
- Loss of Lock Detection and Reporting Pin
- Industrial -40 to +85°C Temperature Range
-
2.0 KV HBM ESD
- Compact, Standard 80-Pin LQFP Package
C544419 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |