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MDD(Microdiode Semiconductor) 74LVC32APW
| Manufacturer | MDD(Microdiode Semiconductor)Asian Brands |
| MPN | 74LVC32APW |
| LCSC Part # | C54411082 |
| Packaging | TSSOP-14L |
| Customer # | |
| Key Attributes | 1.65V~5.5V 5ns@5.5V,15pF 10nA TSSOP-14L Gates and Inverters RoHS |
| Datasheet |  MDD(Microdiode Semiconductor) 74LVC32APW |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | MDD(Microdiode Semiconductor) | |
| Packaging | TSSOP-14L | |
| Logic Family | 74LVC | |
| Voltage - Supply | 1.65V~5.5V | |
| Propagation Delay | 5ns@5.5V,15pF | |
| Output Logic Level - Low | 100mV;300mV;400mV;450mV;550mV;800mV | |
| Input Logic Level - Low | - | |
| Input Logic Level - High | - | |
| Features | - | |
| Operating Temperature | -40℃~+125℃ | |
| Output Logic Level - High | 1.2V;1.9V;2.2V;2.4V;3.8V | |
| Quiescent Current(Iq) | 10nA | |
| Current - Output High(IOH) | - | |
| Number of Channels | 4;2 | |
| Current - Output Low(IOL) | - |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC32A is a quad 2-input OR gate. The inputs can be driven by 3.3 V or 5 V devices. This feature allows these devices to be used as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action on all inputs enables the circuit to tolerate slower input rise and fall times. The device is fully specified for partial-power-down applications using IOFF. The IOFF circuit disables the outputs, preventing potentially damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range: 1.2 V ~ 5.5 V
- Overvoltage-tolerant inputs up to 5.5 V
- CMOS low power consumption
- IOFF circuit for partial power-down mode operation
- Latch-up performance exceeds 250 mA
- Direct TTL-level interface compatible
- JEDEC standard compliant:
- JESD8-7A (1.65 V ~ 1.95 V)
- JESD8-5A (2.3 V ~ 2.7 V)
- JESD8-C (2.7 V ~ 3.6 V)
- JESD36 (4.5 V ~ 5.5 V)
- ESD protection:
- HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000 V
- CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
- Multiple package options
| Qty | Unit Price | Total Amount |
|---|---|---|
| 5+ | $ 0.154 | $ 0.77 |
| 50+ | $ 0.1218 | $ 6.09 |
| 150+ | $ 0.108 | $ 16.20 |
| 500+ | $ 0.0908 | $ 45.40 |
| 2,500+ | $ 0.0832 | $ 208.00 |
| 5,000+ | $ 0.0786 | $ 393.00 |
Standard Packaging2500/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | MDD(Microdiode Semiconductor) | |
| Packaging | TSSOP-14L | |
| Logic Family | 74LVC | |
| Voltage - Supply | 1.65V~5.5V | |
| Propagation Delay | 5ns@5.5V,15pF | |
| Output Logic Level - Low | 100mV;300mV;400mV;450mV;550mV;800mV | |
| Input Logic Level - Low | - | |
| Input Logic Level - High | - | |
| Features | - | |
| Operating Temperature | -40℃~+125℃ | |
| Output Logic Level - High | 1.2V;1.9V;2.2V;2.4V;3.8V | |
| Quiescent Current(Iq) | 10nA | |
| Current - Output High(IOH) | - | |
| Number of Channels | 4;2 | |
| Current - Output Low(IOL) | - |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC32A is a quad 2-input OR gate. The inputs can be driven by 3.3 V or 5 V devices. This feature allows these devices to be used as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action on all inputs enables the circuit to tolerate slower input rise and fall times. The device is fully specified for partial-power-down applications using IOFF. The IOFF circuit disables the outputs, preventing potentially damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range: 1.2 V ~ 5.5 V
- Overvoltage-tolerant inputs up to 5.5 V
- CMOS low power consumption
- IOFF circuit for partial power-down mode operation
- Latch-up performance exceeds 250 mA
- Direct TTL-level interface compatible
- JEDEC standard compliant:
- JESD8-7A (1.65 V ~ 1.95 V)
- JESD8-5A (2.3 V ~ 2.7 V)
- JESD8-C (2.7 V ~ 3.6 V)
- JESD36 (4.5 V ~ 5.5 V)
- ESD protection:
- HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000 V
- CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
- Multiple package options
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |