JSMSEMI 74HC4017D,653-JSM

HC4017 is a 5-stage Johnson decade counter featuring ten spike-free decoded active-HIGH outputs (Q0 to Q9), an active-LOW carry output from the most significant flip-flop (Q5-9), active-HIGH and active-LOW clock inputs (CP0, CP1), and an asynchronous master reset input (MR). The counter is incremented by a LOW-to-HIGH transition on CP0 when CP1 is LOW, or by a HIGH-to-LOW transition on CP1 (overbar) when CP0 is HIGH. For cascading counters, the Q5-9 output (LOW when the counter is in states 5, 6, 7, 8, and 9) can be used to drive the CP0 input of the next stage. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW), independent of the clock inputs (CP0, CP1). Internal circuitry provides automatic counter code correction: following any illegal code, the counter will return to the correct counting sequence within 11 clock pulses. The recommended supply voltage range is 3V to 15V with respect to VSS (typically ground). Unused inputs must be connected to VDD, VSS, or another input.

• Wide supply voltage range: 3V to 15V
• Automatic counter correction
• Tolerant of slow clock rise and fall times
• 5V, 10V, and 15V parametric ratings
• Standardized symmetrical output characteristics
• Operating temperature range: -40℃ to +125℃
• Package options: DIP16/SOP16/TSSOP16