JSMSEMI SN74AUP1G74DCUR-JSM

The 74AUP1G74 is a low-power, low-voltage single positive-edge-triggered D flip-flop with separate data input, clock input, set input, and reset input, along with complementary Q and Q̄ outputs. Set and reset are asynchronous active-LOW inputs that operate independently of the clock input. Data present at the data input is transferred to the Q output on the rising edge of the clock. For predictable operation, the data input must be stable for one setup time prior to the rising edge. Schmitt-trigger inputs on all pins allow the circuit to tolerate slower input rise and fall times across a supply voltage range of 1.8V to 3.6V. The device ensures ultralow static and dynamic power consumption over the entire V_CC supply voltage range of 0.8V to 3.6V. The I_OFF circuitry makes the device fully suitable for applications requiring partial power-down. The I_OFF circuit disables the outputs to prevent damaging backflow current into the circuit during power-down.

• Wide supply voltage range: 0.8V ~ 3.6V
• Low quiescent current: Icc = 1 μA (max)
• Input voltage tolerant up to 3.6V
• IOFF circuitry supports partial power-down mode
• Wide operating temperature range: -40℃ ~ +125℃
• Package: VSSOP8