JSMSEMI HEF4050BT,653-JSM

HEF4050BT,653 - JSM is a 5-stage Johnson decade counter featuring ten spike-free decoded active-high outputs (Q0 to Q9), one active-low carry output from the most significant flip-flop (Q5–9), active-high and active-low clock inputs (CP0, CP1), and a priority asynchronous master reset input (MR). Counting is triggered by a low-to-high transition on CP0 when CP1 is low, or by a high-to-low transition on CP1 when CP0 is high.

When cascading counters, the Q5–9 output goes low during states 5, 6, 7, 8, and 9, and can be used to drive the CP0 input of the next counter. A high level on MR resets the counter to zero (Q0 = Q5–9 = high; Q1 to Q9 = low), regardless of the clock inputs (CP0, CP1).

The internal circuitry provides automatic counter code correction: following any illegal code, the counter returns to normal counting mode within 11 clock pulses.

The recommended supply voltage range for this counter is 3V to 15V with respect to VSS (typically ground). Unused inputs must be connected to VDD, VSS, or another input.

• Wide supply voltage range: 3V to 15V
• Automatic counter correction
• Tolerates slow clock rise and fall times
• Parametric ratings at 5V, 10V, and 15V
• Standardized symmetrical output characteristics
• Operating temperature range: -40℃ to +125℃
• Package: SOP16