TI SN74HC273N

These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

• Wide Operating Voltage Range of δ₂V₀ to 6 V
• Outputs Can Drive Up To 10 LSTTL Loads
• Low Power Consumption, 80 - μA Max ICC
• Typical tpd = 12 ns ±4 - m ± Output Drive at 5 V
• Low Input Current of 1 μA Max
• Contain Eight Flip - Flops With Single - Rail Outputs
• Direct Clear Input
• Individual Data Input to Each Flip - Flop

• Buffer/Storage Registers
• Shift Registers
• Pattern Generators