WCH CH554P

The CH554 is an enhanced E8051 core MCU compatible with the MCS51 instruction set, with 79% of its instructions being single-byte single-cycle, delivering an average instruction speed 8~15 times faster than standard MCS51. It supports a maximum system clock of 24MHz, with 16KB on-chip ROM, 256 bytes of internal iRAM, and 1KB on-chip xRAM with DMA support. The chip integrates ADC, capacitive touch key detection, 3 timers with signal capture and PWM, dual UART, SPI, and supports both USB-Host and USB-Device modes.

• Core: Enhanced E8051 core, MCS51 instruction set compatible, 79% single-byte single-cycle instructions, average speed 8~15x faster than standard MCS51, with XRAM fast data copy instruction and dual DPTR pointers.
• Memory: 16KB multi-programmable ROM, usable entirely as program storage or split into 14KB program area and 2KB boot code area; 128-byte multi-erasable DataFlash; 256-byte internal iRAM; 1KB on-chip xRAM with DMA support.
• USB: Built-in USB controller and transceiver, supports USB-Host and USB-Device modes, USB Type-C master/slave detection, USB 2.0 full-speed 12Mbps or low-speed 1.5Mbps, maximum 64-byte packets, built-in FIFO with DMA support.
• Timers & Signal Processing: 3 timer groups; Timer T2 extended with 2-channel signal capture; 2-channel 8-bit PWM output.
• Serial Communication: 2 UARTs with enhanced baud rate support; SPI controller with built-in FIFO, clock frequency up to half the system clock, master/slave mode support.
• Analog & Sensing: 4-channel 8-bit ADC with voltage comparison; 6-channel capacitive sensing supporting up to 15 touch keys with independent timer interrupts.
• GPIO: Up to 17 GPIO pins.
• Interrupt System: 14 interrupt sources, including 6 standard MCS51-compatible interrupts and 8 extended interrupts.
• System Features: 8-bit programmable watchdog timer with timer interrupt; 4 reset sources; built-in 24MHz clock source with external crystal support; built-in 5V to 3.3V LDO regulator; low-power sleep with multiple wake-up modes; on-chip unique ID.