Nexperia 74LVC2G17GV,125

The 74LVC2G17 is a dual buffer with Schmitt-trigger inputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low-power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• IOFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard: JESD8 - 7 (1.65 V to 1.95 V), JESD8 - 5 (2.3 V to 2.7 V), JESD - 8B/JESD36 (2.7 V to 3.6 V)
• ESD protection: HBM: ANSI/ESDA/JEDEC JS - 001 class 2 exceeds 2000 V; CDM: ANSI/ESDA/JEDEC JS - 002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

• Wave and pulse shapers for highly noisy environments
• Dual non-inverting Schmitt trigger with 5 V tolerant input