HGSEMI CD4094BE

This device is an 8-stage serial shift register with storage latches in each stage, used to gate data from the serial input to the parallel-buffered 3-state outputs QP0 through QP7. The parallel outputs can be connected directly to a common bus. Data shifts on the rising edge of the clock. When the strobe input is high, the data in each shift register stage is transferred to the storage register. When the output enable signal is high, the data in the storage register appears at the outputs. Two serial outputs are provided for cascading multiple devices. Serial data is output from QS1 on the rising edge of the clock for high-speed operation in cascaded systems with fast clock rise times. The same serial data is output from QS2 on the next falling edge of the clock for cascading devices when the clock rise time is slow. The operating supply voltage range is 3V to 15V. Unused inputs must be connected to VDD, VSS, or other inputs.

• Wide supply voltage range: 3V to 15V
• Fully static operation
• 5V, 10V, and 15V parametric ratings
• Standardized symmetrical output characteristics
• Operating temperature range: -40℃ to +125℃
• Package options: DIP16, SOP16, TSSOP16