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HYNIX H5TC2G63GFR-PBK
| Produttore | |
| Cod. Prod. | H5TC2G63GFR-PBK |
| Cod. LCSC | C499915 |
| Imballo | FBGA-96 |
| Numero Cliente | |
| Attr. chiave | 2Gbit 1.6GHz DDR3L SDRAM FBGA-96 Memory |
| Scheda Tecnica | HYNIX H5TC2G63GFR-PBK |
Specifiche del Prodotto
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Memory/Memory | |
| Produttore | HYNIX | |
| Imballo | FBGA-96 | |
| Operating Temperature | -40℃~+105℃ | |
| Features | Auto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Write leveling function | |
| Refresh Current | 9mA | |
| Memory Size | 2Gbit | |
| Voltage - Supply | 1.35V~1.45V;35mA | |
| Clock Frequency | 1.6GHz | |
| Memory Format | DDR3L SDRAM |
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Memory/Memory | |
| Produttore | HYNIX | |
| Imballo | FBGA-96 | |
| Operating Temperature | -40℃~+105℃ | |
| Features | Auto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Write leveling function |
| Tipo | Descrizione | |
|---|---|---|
| Refresh Current | 9mA | |
| Memory Size | 2Gbit | |
| Voltage - Supply | 1.35V~1.45V;35mA | |
| Clock Frequency | 1.6GHz | |
| Memory Format | DDR3L SDRAM |
Descrizione
The H5TC2G83GFR-xxK, H5TC2G63GFR-xxK, H5TC2G83GFR-xxI, H5TC2G63GFR-xxI are a 2Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. SK Hynix DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. SK Hynix 2Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Caratteristiche
- Industrial and Automotive temperature compliant
- VDD = VDDQ = 1.35V + 0.100 / - 0.067V
- Fully differential clock inputs (CK, CK) operation
- Differential Data Strobe (DQS, DQS)
- On chip DLL align DQ, DQS and DQS transition with CK transition
- DM masks write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
- Programmable CAS latency 6, 7, 8, 9, 10, 11, 12 and 13 supported
- Programmable additive latency 0, CL - 1, and CL - 2 supported
- Programmable CAS Write latency (CWL) = 5, 6, 7, 8 and 9
- Programmable burst length 4/8 with both nibble sequential and interleave mode BL switch on the fly
- 8 banks
- Average Refresh Cycle (Tcase 0 ℃ ~ 95 ℃: 7.8 µs at 0 ℃ ~ 85 ℃; 3.9 µs at 85 ℃ ~ 95 ℃; 1.95 μs at 95 ℃ ~ 105 ℃. Operating temperature - Industrial (-40 ℃ ≤ Tcase ≤ +95 ℃), Automotive -40 ℃ ≤ Tcase ≤ +105 ℃)
- JEDEC standard 78 ball FBGA(x8), 96 ball FBGA(x16)
- Driver strength selected by EMRS
- Dynamic On Die Termination supported
- Asynchronous RESET pin supported
- ZQ calibration supported
- TDQS (Termination Data Strobe) supported (x8 only)
- Write Levelization supported
- 8 bit pre - fetch
| Qtà | Pr. unit.(Solo per riferimento) | Importo totale |
|---|---|---|
| 1+ | $ 2.7877 | $ 2.79 |
| 10+ | $ 2.3752 | $ 23.75 |
| 30+ | $ 2.015 | $ 60.45 |
| 100+ | $ 1.7672 | $ 176.72 |
| 500+ | $ 1.6532 | $ 826.60 |
| 1,000+ | $ 1.6009 | $ 1600.90 |
Package Standard1600/Full Tray | ||
Specifiche del Prodotto
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Memory/Memory | |
| Produttore | HYNIX | |
| Imballo | FBGA-96 | |
| Operating Temperature | -40℃~+105℃ | |
| Features | Auto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Write leveling function | |
| Refresh Current | 9mA | |
| Memory Size | 2Gbit | |
| Voltage - Supply | 1.35V~1.45V;35mA | |
| Clock Frequency | 1.6GHz | |
| Memory Format | DDR3L SDRAM |
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Memory/Memory | |
| Produttore | HYNIX | |
| Imballo | FBGA-96 | |
| Operating Temperature | -40℃~+105℃ | |
| Features | Auto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Write leveling function |
| Tipo | Descrizione | |
|---|---|---|
| Refresh Current | 9mA | |
| Memory Size | 2Gbit | |
| Voltage - Supply | 1.35V~1.45V;35mA | |
| Clock Frequency | 1.6GHz | |
| Memory Format | DDR3L SDRAM |
Descrizione
The H5TC2G83GFR-xxK, H5TC2G63GFR-xxK, H5TC2G83GFR-xxI, H5TC2G63GFR-xxI are a 2Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. SK Hynix DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. SK Hynix 2Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Caratteristiche
- Industrial and Automotive temperature compliant
- VDD = VDDQ = 1.35V + 0.100 / - 0.067V
- Fully differential clock inputs (CK, CK) operation
- Differential Data Strobe (DQS, DQS)
- On chip DLL align DQ, DQS and DQS transition with CK transition
- DM masks write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
- Programmable CAS latency 6, 7, 8, 9, 10, 11, 12 and 13 supported
- Programmable additive latency 0, CL - 1, and CL - 2 supported
- Programmable CAS Write latency (CWL) = 5, 6, 7, 8 and 9
- Programmable burst length 4/8 with both nibble sequential and interleave mode BL switch on the fly
- 8 banks
- Average Refresh Cycle (Tcase 0 ℃ ~ 95 ℃: 7.8 µs at 0 ℃ ~ 85 ℃; 3.9 µs at 85 ℃ ~ 95 ℃; 1.95 μs at 95 ℃ ~ 105 ℃. Operating temperature - Industrial (-40 ℃ ≤ Tcase ≤ +95 ℃), Automotive -40 ℃ ≤ Tcase ≤ +105 ℃)
- JEDEC standard 78 ball FBGA(x8), 96 ball FBGA(x16)
- Driver strength selected by EMRS
- Dynamic On Die Termination supported
- Asynchronous RESET pin supported
- ZQ calibration supported
- TDQS (Termination Data Strobe) supported (x8 only)
- Write Levelization supported
- 8 bit pre - fetch
C499915 Libreria EasyEDA
Conformità & Codici di Esportazione
| Tipo | Dettagli |
|---|---|
| ECCN | - |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Tipo | Dettagli |
|---|---|
| ECCN | - |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Tipo | Dettagli |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |