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EnergyMath EM74LVC00APW
| 제조업체 | EnergyMathAsian Brands |
| 제조사 품번 | EM74LVC00APW |
| LCSC 번호 | C49188183 |
| 포장 | TSSOP-14L |
| 고객 번호 | |
| 주요 제원 | Schmitt trigger 1.65V~5.5V 5.5ns@4.5V~5.5V,15pF 40uA TSSOP-14L Gates and Inverters |
| 데이터시트 | EnergyMath EM74LVC00APW |
제품 사양
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| 제조업체 | EnergyMath | |
| 포장 | TSSOP-14L | |
| output type | - | |
| Input Type | Schmitt trigger | |
| Logic Family | 74LVC | |
| Voltage - Supply | 1.65V~5.5V | |
| Output Logic Level - Low | - | |
| Propagation Delay | 5.5ns@4.5V~5.5V,15pF | |
| Input Logic Level - Low | 120mV;700mV;800mV | |
| Input Logic Level - High | 1.08V;1.7V;2V | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Operating Temperature | -40℃~+125℃ | |
| Output Logic Level - High | - | |
| Quiescent Current(Iq) | 40uA | |
| Current - Output High(IOH) | 32mA | |
| Number of Channels | 4;2 | |
| Current - Output Low(IOL) | 32mA |
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| 제조업체 | EnergyMath | |
| 포장 | TSSOP-14L | |
| output type | - | |
| Input Type | Schmitt trigger | |
| Logic Family | 74LVC | |
| Voltage - Supply | 1.65V~5.5V | |
| Output Logic Level - Low | - | |
| Propagation Delay | 5.5ns@4.5V~5.5V,15pF |
| 타입 | 설명 | |
|---|---|---|
| Input Logic Level - Low | 120mV;700mV;800mV | |
| Input Logic Level - High | 1.08V;1.7V;2V | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Operating Temperature | -40℃~+125℃ | |
| Output Logic Level - High | - | |
| Quiescent Current(Iq) | 40uA | |
| Current - Output High(IOH) | 32mA | |
| Number of Channels | 4;2 | |
| Current - Output Low(IOL) | 32mA |
개요
The EM74LVC00A is a quad 2-input NAND gate. Its inputs can be driven by 3.3V or 5V devices. This feature allows the device to be used as a level translator in mixed 3.3V and 5V environments. All inputs incorporate Schmitt-trigger action, enabling the circuit to tolerate slow input rise and fall times. The device fully supports partial power-down applications using the IOFF circuit. The IOFF circuit disables the outputs when the device is powered down, preventing potentially damaging reverse current from flowing through the device.
주요 특징
- Wide supply voltage range: 1.2V to 5.5V
- Input overvoltage tolerance up to 5.5V
- CMOS low power consumption
- I<sub>OFF</sub> circuitry supports partial power-down mode operation
- Latch-up performance exceeds 250mA
- Direct interface with TTL levels
- JEDEC compliant: JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V), JESD36 (4.5V to 5.5V)
- ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000V
- Multiple package options
| 수량 | 단가 | 총액 |
|---|---|---|
| 5+ | $ 0.1561 | $ 0.78 |
| 50+ | $ 0.1226 | $ 6.13 |
| 150+ | $ 0.1082 | $ 16.23 |
| 500+ | $ 0.0903 | $ 45.15 |
| 3,000+ | $ 0.0823 | $ 246.90 |
| 6,000+ | $ 0.0775 | $ 465.00 |
표준 패키지3000/Full Reel | ||
제품 사양
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| 제조업체 | EnergyMath | |
| 포장 | TSSOP-14L | |
| output type | - | |
| Input Type | Schmitt trigger | |
| Logic Family | 74LVC | |
| Voltage - Supply | 1.65V~5.5V | |
| Output Logic Level - Low | - | |
| Propagation Delay | 5.5ns@4.5V~5.5V,15pF | |
| Input Logic Level - Low | 120mV;700mV;800mV | |
| Input Logic Level - High | 1.08V;1.7V;2V | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Operating Temperature | -40℃~+125℃ | |
| Output Logic Level - High | - | |
| Quiescent Current(Iq) | 40uA | |
| Current - Output High(IOH) | 32mA | |
| Number of Channels | 4;2 | |
| Current - Output Low(IOL) | 32mA |
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| 제조업체 | EnergyMath | |
| 포장 | TSSOP-14L | |
| output type | - | |
| Input Type | Schmitt trigger | |
| Logic Family | 74LVC | |
| Voltage - Supply | 1.65V~5.5V | |
| Output Logic Level - Low | - | |
| Propagation Delay | 5.5ns@4.5V~5.5V,15pF |
| 타입 | 설명 | |
|---|---|---|
| Input Logic Level - Low | 120mV;700mV;800mV | |
| Input Logic Level - High | 1.08V;1.7V;2V | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Operating Temperature | -40℃~+125℃ | |
| Output Logic Level - High | - | |
| Quiescent Current(Iq) | 40uA | |
| Current - Output High(IOH) | 32mA | |
| Number of Channels | 4;2 | |
| Current - Output Low(IOL) | 32mA |
개요
The EM74LVC00A is a quad 2-input NAND gate. Its inputs can be driven by 3.3V or 5V devices. This feature allows the device to be used as a level translator in mixed 3.3V and 5V environments. All inputs incorporate Schmitt-trigger action, enabling the circuit to tolerate slow input rise and fall times. The device fully supports partial power-down applications using the IOFF circuit. The IOFF circuit disables the outputs when the device is powered down, preventing potentially damaging reverse current from flowing through the device.
주요 특징
- Wide supply voltage range: 1.2V to 5.5V
- Input overvoltage tolerance up to 5.5V
- CMOS low power consumption
- I<sub>OFF</sub> circuitry supports partial power-down mode operation
- Latch-up performance exceeds 250mA
- Direct interface with TTL levels
- JEDEC compliant: JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V), JESD36 (4.5V to 5.5V)
- ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000V
- Multiple package options
C49188183 EasyEDA 라이브러리
컴플라이언스 & 수출 코드
| 타입 | 세부사항 |
|---|---|
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| 타입 | 세부사항 |
|---|---|
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| 타입 | 세부사항 |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |