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EnergyMath EM74LVC06APW
| Manufacturer | EnergyMathAsian Brands |
| MPN | EM74LVC06APW |
| LCSC Part # | C49188177 |
| Packaging | TSSOP-14L |
| Customer # | |
| Key Attributes | Schmitt trigger 1.65V~5.5V 5ns@5.5V,15pF 6 40uA TSSOP-14L Gates and Inverters RoHS |
| Datasheet |  EnergyMath EM74LVC06APW |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | EnergyMath | |
| Packaging | TSSOP-14L | |
| Input Type | Schmitt trigger | |
| Logic Family | 74LVC | |
| Voltage - Supply | 1.65V~5.5V | |
| Propagation Delay | 5ns@5.5V,15pF | |
| Output Logic Level - Low | 650mV;450mV;600mV;800mV | |
| Input Logic Level - High | 1.08V;1.7V;2V | |
| Input Logic Level - Low | 120mV;700mV;800mV | |
| Operating Temperature | -40℃~+125℃ | |
| Number of Circuits | 6 | |
| Output Logic Level - High | - | |
| Quiescent Current(Iq) | 40uA | |
| Current - Output High(IOH) | - | |
| Number of Channels | - | |
| Current - Output Low(IOL) | - |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC06A provides six inverting buffers with open-drain outputs that can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. The inputs can be driven by 3.3V or 5V devices, making this device suitable for use as a level translator in mixed 3.3V/5V environments. All inputs feature Schmitt-trigger action, making the circuit tolerant of slower input rise and fall times. The device fully supports partial power-down applications using the IOFF circuit, which disables the outputs when the device is powered down, preventing damaging backflow current through the device.
Features
- Wide supply voltage range: 1.2V to 5.5V
- Input overvoltage tolerance up to 5.5V
- CMOS low power consumption
- I<sub>OFF</sub> circuitry supports partial power-down mode operation
- Latch-up performance exceeds 250mA
- Direct TTL-level interface compatible
- JEDEC standards compliant: JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V), JESD36 (4.5V to 5.5V)
- ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000V
- Multiple package options
| Qty | Unit Price | Total Amount |
|---|---|---|
| 5+ | $ 0.1529 | $ 0.76 |
| 50+ | $ 0.1196 | $ 5.98 |
| 150+ | $ 0.1053 | $ 15.80 |
| 500+ | $ 0.0875 | $ 43.75 |
| 3,000+ | $ 0.0796 | $ 238.80 |
| 6,000+ | $ 0.0748 | $ 448.80 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | EnergyMath | |
| Packaging | TSSOP-14L | |
| Input Type | Schmitt trigger | |
| Logic Family | 74LVC | |
| Voltage - Supply | 1.65V~5.5V | |
| Propagation Delay | 5ns@5.5V,15pF | |
| Output Logic Level - Low | 650mV;450mV;600mV;800mV | |
| Input Logic Level - High | 1.08V;1.7V;2V | |
| Input Logic Level - Low | 120mV;700mV;800mV | |
| Operating Temperature | -40℃~+125℃ | |
| Number of Circuits | 6 | |
| Output Logic Level - High | - | |
| Quiescent Current(Iq) | 40uA | |
| Current - Output High(IOH) | - | |
| Number of Channels | - | |
| Current - Output Low(IOL) | - |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC06A provides six inverting buffers with open-drain outputs that can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. The inputs can be driven by 3.3V or 5V devices, making this device suitable for use as a level translator in mixed 3.3V/5V environments. All inputs feature Schmitt-trigger action, making the circuit tolerant of slower input rise and fall times. The device fully supports partial power-down applications using the IOFF circuit, which disables the outputs when the device is powered down, preventing damaging backflow current through the device.
Features
- Wide supply voltage range: 1.2V to 5.5V
- Input overvoltage tolerance up to 5.5V
- CMOS low power consumption
- I<sub>OFF</sub> circuitry supports partial power-down mode operation
- Latch-up performance exceeds 250mA
- Direct TTL-level interface compatible
- JEDEC standards compliant: JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V), JESD36 (4.5V to 5.5V)
- ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000V
- Multiple package options
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |