LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Cart
EnergyMath EM74LVC1G02GX product image
  • EM74LVC1G02GX thumbnail 1
  • EM74LVC1G02GX thumbnail 2
  • EM74LVC1G02GX thumbnail 3
  • Pinout
  • Footprint
Images for reference only

EnergyMath EM74LVC1G02GXRoHS

Manufacturer
EnergyMathAsian Brands
MPN
EM74LVC1G02GX
LCSC Part #
C49188157
Packaging
DFN-4L(0.8x0.8)
Customer #
Key Attributes
Single 2-input NOR gate
Datasheetpdf iconEnergyMath EM74LVC1G02GX
In-Stock: 2,900
2,900 In stock, ships now
Minimum: 5Multiple: 5Sales Unit: Piece
Add to BOM List
QtyUnit PriceTotal Amount
5+$ 0.0892$ 0.45
50+$ 0.0709$ 3.55
150+$ 0.0618$ 9.27
500+$ 0.055$ 27.50
3,000+$ 0.0495$ 148.50
6,000+$ 0.0468$ 280.80
Standard Packaging3000/Full Reel
Better price for more quantity?
$

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerEnergyMath
PackagingDFN-4L(0.8x0.8)
output type-
Input TypeSchmitt trigger;TTL compatible CMOS
Logic Family74LVC
Voltage - Supply1.65V~5.5V
Output Logic Level - Low-
Propagation Delay3.8ns@5.5V,50pF
Input Logic Level - High-
Input Logic Level - Low-
FeaturesLocal shutdown mode;Overvoltage-tolerant input
Operating Temperature-40℃~+125℃
Output Logic Level - High-
Quiescent Current(Iq)4uA
Current - Output High(IOH)24mA
Number of Channels1;2
Current - Output Low(IOL)24mA
Report an ErrorShow similar products (0) >

Introduction

AI Translation

The EM74LVC1G02 is a single 2-input NOR gate. Its inputs can be driven by 3.3V or 5V devices. This feature allows these devices to be used as level translators in mixed 3.3V and 5V environments. Schmitt-trigger action on all inputs makes the circuit tolerant of slower input rise and fall times. The device is fully specified for partial power-down applications using IOFF. The IOFF circuit disables the outputs, preventing potentially damaging reverse current flow through the device when it is powered down.

Features

AI Translation
  • Wide supply voltage range: 1.65 V to 5.5 V
  • Overvoltage-tolerant inputs up to 5.5 V
  • High noise immunity
  • CMOS low power consumption
  • IOFF circuitry supports partial power-down mode operation
  • Output drive capability ±24 mA (VCC = 3.0 V)
  • Latch-up performance exceeds 100 mA
  • Direct TTL-level interface
  • JEDEC compliant: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
  • ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V, MM JESD22-A115C Class C exceeds 550 V, CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
  • Multiple package options