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EnergyMath EM74LVC32APW
| Manufacturer | EnergyMathAsian Brands |
| MPN | EM74LVC32APW |
| LCSC Part # | C49188086 |
| Packaging | TSSOP-14L |
| Customer # | |
| Key Attributes | Quad 2-input OR gate |
| Datasheet |  EnergyMath EM74LVC32APW |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | EnergyMath | |
| Packaging | TSSOP-14L | |
| Logic Family | 74LVC | |
| Voltage - Supply | 1.65V~5.5V | |
| Propagation Delay | 5.5ns@5.5V,15pF | |
| Output Logic Level - Low | 100mV;450mV;300mV;400mV;550mV | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Input Logic Level - Low | 120mV;700mV;800mV | |
| Operating Temperature | -40℃~+125℃ | |
| Input Logic Level - High | 1.08V;1.7V;2V | |
| Output Logic Level - High | 1.2V;1.9V;2.2V;2.4V;3.8V | |
| Quiescent Current(Iq) | 40uA | |
| Current - Output High(IOH) | 32mA | |
| Number of Channels | 4;2 | |
| Current - Output Low(IOL) | 32mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The EM74LVC32A is a quad 2-input OR gate. Its inputs can be driven by 3.3V or 5V devices. This feature allows the device to be used as a level translator in mixed 3.3V and 5V environments. All inputs feature Schmitt-trigger action, enabling the circuit to tolerate slower input rise and fall times. The device fully supports partial power-down applications using the IOFF circuit. The IOFF circuit disables the outputs, preventing potentially destructive backflow currents when the device is powered down.
Features
- Wide supply voltage range: 1.2 V ~ 5.5 V
- Input overvoltage tolerance up to 5.5 V
- CMOS low power consumption
- I<sub>OFF</sub> circuitry for partial power-down mode operation
- Latch-up performance exceeds 250 mA
- Direct TTL-level interface compatible
- JEDEC standards compliant: JESD8-7A (1.65 V to 1.95 V), JESD8-5A (2.3 V to 2.7 V), JESD8-C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
- ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000 V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
- Multiple package options
| Qty | Unit Price | Total Amount |
|---|---|---|
| 5+ | $ 0.1139 | $ 0.57 |
| 50+ | $ 0.1 | $ 5.00 |
| 150+ | $ 0.0941 | $ 14.12 |
| 500+ | $ 0.0867 | $ 43.35 |
| 3,000+ | $ 0.0834 | $ 250.20 |
| 6,000+ | $ 0.0814 | $ 488.40 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | EnergyMath | |
| Packaging | TSSOP-14L | |
| Logic Family | 74LVC | |
| Voltage - Supply | 1.65V~5.5V | |
| Propagation Delay | 5.5ns@5.5V,15pF | |
| Output Logic Level - Low | 100mV;450mV;300mV;400mV;550mV | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Input Logic Level - Low | 120mV;700mV;800mV | |
| Operating Temperature | -40℃~+125℃ | |
| Input Logic Level - High | 1.08V;1.7V;2V | |
| Output Logic Level - High | 1.2V;1.9V;2.2V;2.4V;3.8V | |
| Quiescent Current(Iq) | 40uA | |
| Current - Output High(IOH) | 32mA | |
| Number of Channels | 4;2 | |
| Current - Output Low(IOL) | 32mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The EM74LVC32A is a quad 2-input OR gate. Its inputs can be driven by 3.3V or 5V devices. This feature allows the device to be used as a level translator in mixed 3.3V and 5V environments. All inputs feature Schmitt-trigger action, enabling the circuit to tolerate slower input rise and fall times. The device fully supports partial power-down applications using the IOFF circuit. The IOFF circuit disables the outputs, preventing potentially destructive backflow currents when the device is powered down.
Features
- Wide supply voltage range: 1.2 V ~ 5.5 V
- Input overvoltage tolerance up to 5.5 V
- CMOS low power consumption
- I<sub>OFF</sub> circuitry for partial power-down mode operation
- Latch-up performance exceeds 250 mA
- Direct TTL-level interface compatible
- JEDEC standards compliant: JESD8-7A (1.65 V to 1.95 V), JESD8-5A (2.3 V to 2.7 V), JESD8-C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
- ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000 V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
- Multiple package options
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |