MaxLinear XRT83SL30IV-F

The XRT83SL30 is a fully integrated single-channel short-haul line interface unit for T1 (1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or 120Ω, and J1 110Ω applications. In T1 applications, the device generates five transmit pulse waveforms to meet DSX-1 template requirements. It provides a serial host microprocessor interface and hardware mode for programming and control. Built-in B8ZS and HDB3 codec functionality can be disabled as needed. The on-chip crystal-less jitter attenuator features a 32-bit or 64-bit FIFO that can be placed in the receive or transmit path, with a loop bandwidth of less than 3Hz. The device offers multiple loopback and diagnostic functions, as well as transmit driver short-circuit detection and receive loss-of-signal monitoring. It supports internal impedance matching for both transmitter and receiver at 75Ω, 100Ω, 110Ω, and 120Ω. For the receiver, termination can be achieved via internal resistors or a combination of a single fixed-value external resistor and a programmable internal resistor. When power is removed, the transmit outputs and receive inputs enter a tri-state condition, making it suitable for redundancy applications. The chip integrates a programmable clock multiplier capable of synthesizing T1 or E1 master clocks from multiple external clock sources.

• Fully integrated, single-channel short-haul transceiver for E1, T1, or J1 applications
• Programmable transmit pulse shaper for E1, T1, or J1 short-haul interfaces
• Five fixed transmit pulse settings for T1 short-haul applications
• High receive interference immunity
• Receive monitor mode handles 0 to 29dB resistive attenuation and 0 to 6dB cable attenuation for T1 and E1 modes
• Supports 75Ω and 120Ω (E1), 100Ω (T1), and 110Ω (J1) applications
• Internal and/or external impedance matching for 75Ω, 100Ω, 110Ω, and 120Ω
• Tri-state transmit output and receive input capability for redundant applications
• High impedance on transmit and receive during power-down
• Transmit return loss meets or exceeds ETSI 300 166
• On-chip digital clock recovery with high input jitter tolerance
• Crystal-free digital jitter attenuator with 32-bit or 64-bit FIFO, selectable in transmit or receive path
• On-chip frequency multiplier generates T1 or E1 master clock from multiple external clock sources
• On-chip transmit short-circuit protection and current limiting with driver fault monitor output
• Receive loss-of-signal output
• On-chip HDB3/B8ZS/AMI encoder/decoder
• QRSS pattern generation and detection for test and monitoring
• Bit error and bipolar violation insertion and detection
• Receive line attenuation indication output in 1dB steps
• Network loopcode detection for automatic loopback activation/deactivation
• All-ones transmit and in-band network loopback activation/deactivation code generator
• Supports local analog, remote, digital, and dual loopback modes
• Meets or exceeds T1 and E1 short-haul network access specifications
• Hardware and serial microprocessor interface programming support
• Programmable interrupts
• Low power consumption
• Logic inputs compatible with 3.3V or 5V levels
• Single +3.3V supply
• 64-pin TQFP package
• Operating temperature range: -40°C to +85°C

• T1 digital cross-connect
• ISDN primary rate interface
• CSU/DSU E1/T1/J1 interface
• T1/E1/J1 LAN/WAN router
• Public switching systems and PBX interface