XBLW SN74LS259N(XBLW)
| Manufacturer | XBLWAsian Brands |
| MPN | SN74LS259N(XBLW) |
| LCSC Part # | C47021212 |
| Packaging | DIP-16 |
| Customer # | |
| Key Attributes | 8-bit addressable latch |
| Datasheet |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | XBLW | |
| Packaging | DIP-16 | |
| Quiescent Current | 8uA | |
| Series | 74LS | |
| Logic Type | Addressable Latch | |
| Voltage - Supply | 2V~6V | |
| Output Type | - | |
| Operating Temperature | -20℃~+85℃ | |
| Current - Output Low(IOL) | - | |
| Setup Time | 7ns | |
| Current - Output High(IOH) | - | |
| Number of Gates | 8 | |
| Hold Time | 0ns;2ns | |
| Propagation Delay | 17ns |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | XBLW | |
| Packaging | DIP-16 | |
| Quiescent Current | 8uA | |
| Series | 74LS | |
| Logic Type | Addressable Latch | |
| Voltage - Supply | 2V~6V | |
| Output Type | - |
| Type | Description | |
|---|---|---|
| Operating Temperature | -20℃~+85℃ | |
| Current - Output Low(IOL) | - | |
| Setup Time | 7ns | |
| Current - Output High(IOH) | - | |
| Number of Gates | 8 | |
| Hold Time | 0ns;2ns | |
| Propagation Delay | 17ns |
Introduction
The SN74LS259 is an 8-bit addressable latch. The device features four operating modes. In the addressable latch mode, data at the D input is written into the latch addressed by the A0 through A3 inputs. The addressed latch follows the data input, while unaddressed latches retain their previous states. In the memory mode, all latches retain their previous states regardless of data or address inputs. In the 3-line-to-8-line decoding or demultiplexing mode, the addressed output follows the D input while all other outputs are held low. In the reset mode, all outputs are forced low regardless of data or address inputs. The inputs include clamp diodes, which allow the use of current-limiting resistors to interface inputs to voltages exceeding VCC.
Features
- Combined demultiplexer and 8-bit latch
- Serial-to-parallel conversion capability
- Individual output access for each storage bit
- Random (addressable) data input
- Easy cascade expansion
- Common reset input
- Usable as 3-line to 8-line active-high decoder
- Operating temperature range: -20°C ~ +85°C
- Package options: DIP-16 / SOP-16 / TSSOP-16
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.7119$ 0.6764 | $ 0.68 |
| 10+ | $ 0.5761$ 0.5473 | $ 5.47 |
| 25+ | $ 0.5089$ 0.4835 | $ 12.09 |
| 100+ | $ 0.4418$ 0.4198 | $ 41.98 |
| 500+ | $ 0.4028$ 0.3827 | $ 191.35 |
| 1,000+ | $ 0.3809$ 0.3619 | $ 361.90 |
Standard Packaging25/Full Tube | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | XBLW | |
| Packaging | DIP-16 | |
| Quiescent Current | 8uA | |
| Series | 74LS | |
| Logic Type | Addressable Latch | |
| Voltage - Supply | 2V~6V | |
| Output Type | - | |
| Operating Temperature | -20℃~+85℃ | |
| Current - Output Low(IOL) | - | |
| Setup Time | 7ns | |
| Current - Output High(IOH) | - | |
| Number of Gates | 8 | |
| Hold Time | 0ns;2ns | |
| Propagation Delay | 17ns |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | XBLW | |
| Packaging | DIP-16 | |
| Quiescent Current | 8uA | |
| Series | 74LS | |
| Logic Type | Addressable Latch | |
| Voltage - Supply | 2V~6V | |
| Output Type | - |
| Type | Description | |
|---|---|---|
| Operating Temperature | -20℃~+85℃ | |
| Current - Output Low(IOL) | - | |
| Setup Time | 7ns | |
| Current - Output High(IOH) | - | |
| Number of Gates | 8 | |
| Hold Time | 0ns;2ns | |
| Propagation Delay | 17ns |
Introduction
The SN74LS259 is an 8-bit addressable latch. The device features four operating modes. In the addressable latch mode, data at the D input is written into the latch addressed by the A0 through A3 inputs. The addressed latch follows the data input, while unaddressed latches retain their previous states. In the memory mode, all latches retain their previous states regardless of data or address inputs. In the 3-line-to-8-line decoding or demultiplexing mode, the addressed output follows the D input while all other outputs are held low. In the reset mode, all outputs are forced low regardless of data or address inputs. The inputs include clamp diodes, which allow the use of current-limiting resistors to interface inputs to voltages exceeding VCC.
Features
- Combined demultiplexer and 8-bit latch
- Serial-to-parallel conversion capability
- Individual output access for each storage bit
- Random (addressable) data input
- Easy cascade expansion
- Common reset input
- Usable as 3-line to 8-line active-high decoder
- Operating temperature range: -20°C ~ +85°C
- Package options: DIP-16 / SOP-16 / TSSOP-16
C47021212 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



