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TI SN74AC74DR
| Manufacturer | |
| MPN | SN74AC74DR |
| LCSC Part # | C352945 |
| Packaging | SOIC-14 |
| Customer # | |
| Key Attributes | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET |
| Datasheet |  TI SN74AC74DR |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SOIC-14 | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 2V~6V | |
| Number of Bits per Element | 1 | |
| Series | 74AC Series | |
| Output Type | Complementary type | |
| Number of Elements | 2 | |
| Current - Output High(IOH) | 24mA | |
| Current - Output Low(IOL) | 24mA | |
| Setup Time | 3ns | |
| Quiescent Current | 2uA | |
| Hold Time | 500ps | |
| Propagation Delay | 6ns@5V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The ’AC74 devices are dual positive-edge triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.
| Qty | Unit Price | Total Amount |
|---|---|---|
| 5+ | $ 0.1915 | $ 0.96 |
| 50+ | $ 0.1457 | $ 7.29 |
| 150+ | $ 0.1261 | $ 18.92 |
| 500+ | $ 0.1016 | $ 50.80 |
| 2,500+ | $ 0.0907 | $ 226.75 |
| 5,000+ | $ 0.0842 | $ 421.00 |
Standard Packaging2500/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SOIC-14 | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 2V~6V | |
| Number of Bits per Element | 1 | |
| Series | 74AC Series | |
| Output Type | Complementary type | |
| Number of Elements | 2 | |
| Current - Output High(IOH) | 24mA | |
| Current - Output Low(IOL) | 24mA | |
| Setup Time | 3ns | |
| Quiescent Current | 2uA | |
| Hold Time | 500ps | |
| Propagation Delay | 6ns@5V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The ’AC74 devices are dual positive-edge triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |