Rochester Electronics 25LS2519DM/B

The Am25LS2519 consists of four D-type flip-flops with a buffered common clock enable. Data meeting the D input setup and hold time requirements is transferred to the flip-flop outputs on the low-to-high transition of the clock. When the output enable (OE) input is LOW, the data from the flip-flop Q outputs is present at the three-state outputs. When the corresponding OE input is HIGH, the outputs are in the high-impedance state. Two separate sets of outputs — W and Y — are provided, allowing the register to drive two buses simultaneously and independently. One set of outputs includes polarity control, enabling the outputs to be either inverting or non-inverting. The device also features an active-LOW asynchronous clear function. When the clear input is LOW, the Q outputs of the internal flip-flops are forced LOW, regardless of other inputs. The Am25LS2519 is offered in a space-saving 20-pin package with 0.3-inch pin spacing.

• Dual fully buffered tri-state outputs
• Four D-type flip-flops
• Polarity control on W outputs
• Buffered common clock enable
• Buffered common asynchronous clear
• Independent buffered common output enable per output group

• Convenient register content monitoring or test points