Infineon/CYPRESS CY7C455-14JI

CY7C455, CY7C456, and CY7C457 are high-speed, low-power FIFOs with a clocked read/write interface, all 18 bits wide. The CY7C455 features a 512-word memory array, the CY7C456 a 1024-word array, and the CY7C457 a 2048-word array. These devices can be cascaded to increase FIFO depth. Programmable features include almost-full/empty flags and parity generation and checking. These FIFOs provide solutions for a variety of data buffering requirements, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. In both stand-alone and width-expansion configurations, asserting the retransmit input low causes the device to retransmit data. During retransmission, both read enable and write enable must be held high, after which the read enable is used to access data. When write enable is asserted, data is written to the FIFO on the rising edge of the write clock. As long as write enable remains asserted, data continues to be written on every write clock cycle. The output port is controlled in a similar manner by a free-running read clock and a read enable pin. In addition, these devices feature an output enable pin. The read and write clocks can be tied together for single-clock operation, or run independently to support asynchronous read/write applications. Clock frequencies up to 83.3 MHz are supported in stand-alone configuration as well as in depth-expansion cascade. Depth expansion is achieved via cascade-in, cascade-out, and first-load pins. The XO pin connects to the X1 pin of the next device; the XO pin of the last device should be connected to the X1 pin of the first device. The FL pin of the first device is connected to VSS. These devices provide three status pins that, when decoded, indicate one of six states: empty, almost empty, less than or equal to half-full, greater than half-full, almost full, and full. The almost-empty/full flag is multiplexed with the XO pin on the CY7C455, CY7C456, and CY7C457. This flag is valid in stand-alone and width-expansion configurations. In depth-expansion mode, this pin provides expansion output information to notify the next FIFO when to activate. The flags are synchronous in nature — their state changes are relative to either the read clock or the write clock. When entering or exiting the empty and almost-empty states, the flags are updated by the read clock only. Flags indicating the half-full, almost-full, and full states are updated by the write clock only. The synchronous flag architecture ensures that flags maintain their state for a minimum time, which is typically approximately equal to one cycle time. These devices use center power and ground pins to reduce noise. All configurations are fabricated using an advanced 0.65-micron CMOS process. Input ESD protection exceeds 2001V, and latch-up protection is provided by guard rings.

• High-speed, low-power FIFO memories
• 512 × 18 (CY7C455)
• 1024 × 18 (CY7C456)
• 2048 × 18 (CY7C457)
• 0.65-micron CMOS technology for optimized speed-power balance
• High-speed 83 MHz operation (12 ns read/write cycle time)
• Low power, ICC = 90 mA
• Fully asynchronous and simultaneous read/write operation
• Empty, full, half-full, and programmable almost-empty and almost-full flags
• TTL-compatible levels
• Retransmit function
• Parity generation and checking
• Output enable pin
• Separate read enable and write enable pins
• Center power and ground pins for reduced noise
• Free-running 50% duty cycle clock input support
• Width expansion capability
• Depth expansion capability
• 52-pin PLCC and 52-pin PQFP packages

• High-speed data acquisition
• Multi-processor interface
• Communication buffering