Infineon/CYPRESS S25FL128LAGNFI010

The FL-L family devices are flash non-volatile memory products using: Floating gate technology; 65-nm process lithography. The FL-L family connects to a host system via a serial peripheral interface (SPI). Traditional SPI single bit serial input and output (single I/O or SIO) is supported as well as optional two bit (dual I/O or DIO) and four bit wide Quad I/O (QIO) and quad peripheral interface (QPI) commands. In addition, there are double data rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock. The architecture features a page programming buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase. By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories, while reducing signal count dramatically. The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power. These memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM, executing code directly (XIP), and storing re-programmable data.

• SPI with multi-I/O:
  • Clock polarity and phase modes 0 and 3
  • Double data rate (DDR) option
  • Quad peripheral interface (QPI) option
  • Extended addressing: 24- or 32-bit address options
  • Serial command subset and footprint compatible with S25FL-A, S25FL1-K, S25FL-P, S25FL-S and S25FS-S SPI families
  • Multi I/O command subset and footprint compatible with S25FL-P, S25FL-S and S25FS-S SPI families
• Read:
  • Commands: normal, fast, dual I/O, Quad I/O, dualO, QuadO, DDR Quad I/O.
  • Modes: Burst wrap, continuous (XIP), QPI
  • Serial flash discoverable parameters (SFDP) for configuration information.
• Program architecture:
  • 256 bytes page programming buffer
  • 256 Mb (32 MB)/128 Mb (16 MB), 3.0 V FL-L flash memory
  • Program suspend and resume
• Erase architecture:
  • Uniform 4 KB sector erase
  • Uniform 32 KB half block erase
  • Uniform 64 KB block erase
  • Chip erase
  • Erase suspend and resume
• 100,000 program/erase cycles, minimum
• 20 year data retention, minimum
• Security features:
  • Status and Configuration Register protection
  • Four security regions of 256 bytes each outside the main flash array
  • Legacy block protection: Block range
  • Individual and region protection
  • Individual block lock: Volatile individual sector/block
  • Pointer region: Non-volatile sector/block range
  • Power supply lock-down, password, or permanent protection of security regions 2 and 3 and pointer region
• Technology: 65-nm floating gate technology
• Single supply voltage with CMOS I/O: 2.7 V to 3.6 V
• Temperature range / grade:
  • Industrial (-40°C to +85°C)
  • Industrial Plus (-40°C to +105°C)
  • Automotive, AEC-Q100 grade 3 (-40°C to +85°C)
  • Automotive, AEC-Q100 grade 2 (-40°C to +105°C)
  • Automotive, AEC-Q100 grade 1 (-40°C to +125°C)