ESPRESSIF ESP32-S3

ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi and Bluetooth Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor (Xtensa 32-bit LX7), a ULP coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, RF module, and numerous peripherals.

• Wi-Fi:
  • IEEE 802.11b/g/n-compliant
  • Supports 20 MHz and 40 MHz bandwidth in 2.4 GHz band
  • 1T1R mode with data rate up to 150 Mbps
  • Wi-Fi Multimedia (WMM)
  • TX/RX A-MPDU, TX/RX A-MSDU
  • Immediate Block ACK
  • Fragmentation and defragmentation
  • Automatic Beacon monitoring (hardware TSF)
  • Four virtual Wi-Fi interfaces
  • Simultaneous support for Infrastructure BSS in Station, SoftAP, or Station + SoftAP modes
  • Antenna diversity
  • 802.11mc FTM
• Bluetooth:
  • Bluetooth LE: Bluetooth 5, Bluetooth mesh
  • High power mode (20 dBm)
  • Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps
  • Advertising extensions
  • Multiple advertisement sets
  • Channel selection algorithm #2
  • Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna
• CPU and Memory:
  • Xtensa dual-core 32-bit LX7 microprocessor
  • Clock speed: up to 240 MHz
  • CoreMark score: One core at 240 MHz: 613.86 CoreMark; 2.56 CoreMark/MHz; Two cores at 240 MHz: 1181.60 CoreMark; 4.92 CoreMark/MHz
  • Five-stage pipeline
  • 128-bit data bus and dedicated SIMD instructions
  • Single precision floating point unit (FPU)
  • L1 cache
  • ROM: 384 KB
  • SRAM: 512 KB
  • SRAM in RTC: 16 KB
  • Supported SPI protocols: SPI, Dual SPI, Quad SPI, Octal SPI, QPI and OPI interfaces that allow connection to flash, external RAM, and other SPI devices
  • Flash controller with cache is supported
  • Flash in-Circuit Programming (ICP) is supported
• Advanced Peripheral Interfaces:
  • 45 programmable GPIOs
  • Digital interfaces: Two SPI ports for communication with flash and RAM; Two general-purpose SPI ports; LCD interface (8-bit ~ 16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411; DVP 8-bit ~ 16-bit camera interface; Three UARTs; Two I2Cs; Two I2Ss; RMT (TX/RX); Pulse counter; LED PWM controller, up to 8 channels; Full-speed USB OTG; USB Serial/JTAG controller; Two Motor Control PWMs (MCPWM); SD/MMC host controller with 2 slots; General DMA controller (GDMA), with 5 transmit channels and 5 receive channels; TWAI controller, compatible with ISO 11898-1 (CAN Specification 2.0)
  • On-chip debug functionality via JTAG
  • Analog interfaces: Two 12-bit SAR ADCs, up to 20 channels; Temperature sensor; 14 touch sensing IOs
  • Timers: Four 54-bit general-purpose timers; 52-bit system timer; Three watchdog timers
• Low Power Management:
  • Fine-resolution power control through a selection of clock frequency, duty cycle, Wi-Fi operating modes, and individual power control of internal components
  • Four power modes designed for typical scenarios: Active, Modem-sleep, Light-sleep, Deep-sleep
  • Power consumption in Deep-sleep mode is as low as 7 µA
  • Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V coprocessor; ULP-FSM coprocessor
  • RTC memory remains powered on in Deep-sleep mode
• Security:
  • Secure boot
  • Flash encryption
  • 4-Kbit OTP, up to 1792 bits for users
  • Cryptographic hardware acceleration: AES-128/256 (FIPS PUB 197); SHA (FIPS PUB 180-4); RSA; Random Number Generator (RNG); HMAC; Digital signature

• Smart Home
• Industrial Automation
• Health Care
• Consumer Electronics
• Smart Agriculture
• POS machines
• Service robot
• Audio Devices
• Generic Low-power IoT Sensor Hubs
• Generic Low-power IoT Data Loggers
• Cameras for Video Streaming
• USB Devices
• Speech Recognition
• Image Recognition
• Wi-Fi + Bluetooth Networking Card
• Touch and Proximity Sensing