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TI SN74ABT244ADBRRoHS

Manufacturer
MPN
SN74ABT244ADBR
LCSC Part #
C2877480
Packaging
SSOP-20-208mil
Customer #
Key Attributes
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Datasheetpdf iconTI SN74ABT244ADBR
In-Stock: 65
65 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 2.5408$ 2.54
200+$ 1.1031$ 220.62
500+$ 1.0712$ 535.60
1,000+$ 1.0554$ 1055.40
Standard Packaging2000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers
ManufacturerTI
PackagingSSOP-20-208mil
Input type-
Current - Output High(IOH)32mA
Series74ABT
Voltage - Supply4.5V~5.5V
Operating Temperature-40℃~+85℃
Output TypeTri-State
Current - Output Low(IOL)64mA
Number of Bits per Element4
Channel TypeUnidirectional
FeaturesOutput enable
Number of Elements2
Propagation Delay2.9ns@5V,50pF
Quiescent Current250uA

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT240, SN74ABT240A, SN54ABT241, and SN74ABT241A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE(overline)) inputs, and complementary OE and OC(overline) inputs.

The SN54ABT244 and SN74ABT244A are organized as two 4-bit buffers/line drivers with separate OE inputs. When OE(overline) is low, the devices pass noninverted data from the A inputs to the Y outputs. When OC(overline) is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE(overline) should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Features

AI Translation
  • State-of-the-Art EPIC-IIB BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • ESD Protection Exceeds 2000V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model ΔC = 200 pF, R = 0
  • Typical vOLP (Output Ground Bounce) < 1 V at Vcc = 5 V, TA = 25℃
  • High-Drive Outputs (-32-mA loH, 64-mA loL)
  • Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package