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TI SN74LVC573AQPWREP

Manufacturer
MPN
SN74LVC573AQPWREP
LCSC Part #
C2876971
Packaging
TSSOP-20
Customer #
Key Attributes
D Latch 2V~3.6V 8 6.9ns TSSOP-20 Latches RoHS
DatasheetTI SN74LVC573AQPWREP
RoHS Compliance1 documents available
Alternative Parts5
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QtyUnit Price(Reference Only)Total Amount
1+$ 3.1773$ 3.18
200+$ 1.2304$ 246.08
500+$ 1.1876$ 593.80
1,000+$ 1.1654$ 1165.40
Standard Packaging2000/Full Reel
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Latches
ManufacturerTI
PackagingTSSOP-20
Quiescent Current10uA
Series74LVC
Logic TypeD Latch
Voltage - Supply2V~3.6V
Operating Temperature-40℃~+125℃
Current - Output Low(IOL)24mA
Output TypeTri-State
Number of Gates8
Setup Time2ns
Current - Output High(IOH)24mA
Hold Time2.5ns
Propagation Delay6.9ns

Introduction

AI Translation

SN74LVC573A-EP octal transparent D-type latch, designed for 2.7 V to 3.6 V VCC operation. The device features 3-state outputs designed to drive highly capacitive or relatively low-impedance loads, making it especially suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. When the latch enable (LE) input is high, the Q outputs follow the data (D) inputs; when LE goes low, the Q outputs latch the logic levels of the D inputs. The buffered output enable (OE) input can place all eight outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and enhanced drive capability allow bus lines to be driven without interface or pull-up components. OE does not affect the internal operation of the latches; old data can be retained or new data can be entered while the outputs are in the high-impedance state. The device is fully specified for partial-powerdown applications using Ioff; the Ioff circuit disables the outputs, preventing damaging backflow current when the device is powered down. To ensure the high-impedance state during power-up or power-down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven by 3.3 V or 5 V devices, allowing this device to be used as a level translator in mixed 3.3 V/5 V system environments.

Features

AI Translation
  • Controlled baseline
  • Single assembly/test site, single manufacturing site
  • Extended temperature operating range: -40℃ to 125℃
  • Enhanced Diminishing Manufacturing Sources (DMS) support
  • Enhanced product change notification
  • Qualification certification
  • Operating voltage range: 2 V to 3.6 V
  • Inputs accept up to 5.5 V
  • Maximum tpd of 6.9 ns at 3.3 V
  • Typical output ground bounce (VOLP) < 0.8 V at 3.3 V, 25℃
  • Typical output VOH undershoot (VOHV) > 2 V at 3.3 V, 25℃
  • Mixed-mode signal operation on all ports (5 V I/O voltage with 3.3 V VCC)
  • Ioff supports partial power-down mode operation

Applications

AI Translation
  • Buffer register
  • I/O port
  • Bidirectional bus driver
  • Working register

Alternative Parts

MPNManufacturerAlternative TypePackagingAvailabilityUnit Price
SN74LVC573AQPWRQ1TISimilarTSSOP-2028$ 0.506
U74LVC573G-ULA-RUTCSimilarTSSOP-20U500$ 0.3151
SN74LVC373AQPWREPTISimilarTSSOP-209$ 3.5083
SN74LVC373APWTISimilarTSSOP-20113$ 0.8148
SN74LVC573APWRTISimilarTSSOP-20809$ 0.8474
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