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TI LMK00306SQE/NOPB product image
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TI LMK00306SQE/NOPBRoHS

Manufacturer
MPN
LMK00306SQE/NOPB
LCSC Part #
C2866028
Packaging
WQFN-36-EP(6x6)
Customer #
Key Attributes
3GHz, 6-channel output ultra-low added jitter differential clock buffer/level shifter
Datasheetpdf iconTI LMK00306SQE/NOPB
In-Stock: 54
54 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 12.1757$ 12.18
10+$ 10.47$ 104.70
30+$ 9.4309$ 282.93
100+$ 8.561$ 856.10
Standard Packaging250/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Clock/Timing/Clock Buffers, Drivers
ManufacturerTI
PackagingWQFN-36-EP(6x6)
Operating Temperature-40℃~+85℃
Voltage - Supply3.15V~3.45V
FeaturesMulti-channel fan-out/isolation drive;Output enable/shutdown
Number of Inputs3
Output Frequency(Max)3.1GHz
Number of outputs7

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging250
Sales UnitPiece

Introduction

AI Translation

The LMK00306 is a 3GHz, 6-channel output differential fanout buffer used for high-frequency, low-jitter clock/data distribution and level conversion. It can select the input clock from two general-purpose inputs or one crystal oscillator input. The selected input clock is distributed to two output groups, with each group containing 3 differential outputs and 1 LVCMOS output. The two differential output groups can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for glitch-free operation when enabled or disabled. The LMK00306 operates with a 3.3V core power supply and 3 independent 3.3V/2.5V output power supplies. The LMK00306 features high performance, versatility, and power efficiency, making it an ideal choice to replace fixed-output buffer devices while increasing the timing margin in the system.

Features

AI Translation
  • 3:1 input multiplexer
  • Two general-purpose inputs operating up to 3.1GHz, accepting LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clock signal levels
  • One crystal input accepting 10 to 40MHz crystal or single-ended enable clock
  • Two banks of differential outputs, 3 per bank
  • LVPECL, LVDS, HCSL, or Hi-Z (selectable per bank)
  • Additive jitter with LMK03806 clock source at 156.25MHz (LVPECL): 20fs RMS (10kHz to 1MHz), 51fs RMS (12kHz to 20MHz)
  • High PSRR: -65/-76dBc at 156.25MHz (LVPECL/LVDS)
  • LVCMOS output with synchronous enable input
  • Pin-controlled configuration
  • VCC core supply: 3.3V ±5%
  • Three independent VCCO output supplies: 3.3V/2.5V ±5%
  • Industrial temperature range: -40°C to +85°C
  • 36-pin WQFN package (6mm × 6mm)

Applications

AI Translation
  • Clock distribution and level translation for ADC, DAC, multi-gigabit Ethernet, XAUI, Fibre Channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes
  • Switches, routers, line interface cards, timing cards
  • Servers, computing, PCI Express (PCIe 3.0)
  • Remote radio units and base station units