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TI CD4085BERoHS

Manufacturer
MPN
CD4085BE
LCSC Part #
C2860658
Packaging
PDIP-14
Customer #
Key Attributes
CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate
Datasheetpdf iconTI CD4085BE
In-Stock: 88
88 In stock, ships now
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Once stock is depleted, this item will be marked as "Out of Stock."
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QtyUnit PriceTotal Amount
1+$ 0.4716$ 0.47
10+$ 0.3751$ 3.75
25+$ 0.3332$ 8.33
100+$ 0.2817$ 28.17
500+$ 0.2576$ 128.80
1,000+$ 0.2447$ 244.70
Standard Packaging25/Full Tube

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters - Multi-Function, Configurable
ManufacturerTI
PackagingPDIP-14
Logic Family4000B Series
Propagation Delay180ns@15V,50pF
Voltage - Supply3V~18V
Operating Temperature-55℃~+125℃
Output Logic Level - Low50mV;-
Input Logic Level - High3.5V;7V;11V
Input Logic Level - Low1.5V;3V;4V
Current - Output Low(IOL)6.8mA
Output Logic Level - High4.95V;9.95V;14.95V
Quiescent Current(Iq)20nA
Current - Output High(IOH)6.8mA
Features-
Number of Channels2

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging25
Sales UnitPiece

Introduction

AI Translation

CD4085 contains a pair of AND. OR - INVERT gates, each consisting of two 2 - input AND gates driving a 3 - input NOR gate. Individual inhibit controls are provided for both A - O - l gates.

Features

AI Translation
  • Medium - speed operation: tPH = 125 ns (typ.) at 10 V
  • Individual inhibit controls
  • Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V
  • Maximum input current of ±μμ at 18 V over full package - temperature range; 100 nA at ∇M v and 25℃
  • Noise margin (over full package - temperature range): 1 V at vDD = 5 V, 2 V at vDD = 10 V, 2.5 V at vDD = 15 V
  • 5 - V, 10 - V, and 15 - V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. t3B, "Standard Specifications for Description of 'B' Series CMOs Devices"