micron MT53E256M32D2DS-053 WT:B

Products Specifications

Type	Description	All
Category	Integrated Circuits (ICs)/Memory/Memory (ICs)
Manufacturer	micron
Packaging	VFBGA-200
Refresh Current	-
Memory Size	8Gbit
Voltage - Supply	1.1V
Operating temperature	-30℃~+85℃
Clock Frequency	1.866GHz
Features	Auto self-refresh;Built-in temperature sensor;Auto precharge function;Write leveling function;ZQ calibration function
Memory Format	LPDDR4 SDRAM
Current - Supply	-

AI Translation

Ultra-low-voltage core and I/O power supplies – VDD1 = 1.70 - 1.95V; 1.80V nominal – VDD2 = 1.06–1.17V; 1.10V nominal VDDQ = 1.06 - 1.17V; 1.10V nominal or Low VDDQ = 0.57–0.65V; 0.60V nominal
Frequency range – 2133–10 MHz (data rate range: 4266–20 Mb/s/pin)
16n prefetch DDR architecture
8 internal banks per channel for concurrent operation
Single-data-rate CMD/ADR entry
Bidirectional/differential data strobe per byte lane
Programmable READ and WRITE latencies (RL/WL)
Programmable and on-the-fly burst lengths (BL = 16, 32)
Directed per-bank refresh for concurrent bank operation and ease of command scheduling
Up to 8.5 GB/s per die
On-chip temperature sensor to control self refresh rate
Partial-array self refresh (PASR)
Selectable output drive strength (DS)
Clock-stop capability
RoHS-compliant, “green” packaging
Programmable VSS (ODT) termination

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Qty	Unit Price(Reference Only)	Total Amount
1+	$ 27.2294	$ 27.23
Standard Packaging2000/Full Reel

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Type	Description	All
Category	Integrated Circuits (ICs)/Memory/Memory (ICs)
Manufacturer	micron
Packaging	VFBGA-200
Refresh Current	-
Memory Size	8Gbit
Voltage - Supply	1.1V
Operating temperature	-30℃~+85℃
Clock Frequency	1.866GHz
Features	Auto self-refresh;Built-in temperature sensor;Auto precharge function;Write leveling function;ZQ calibration function
Memory Format	LPDDR4 SDRAM
Current - Supply	-

AI Translation

Ultra-low-voltage core and I/O power supplies – VDD1 = 1.70 - 1.95V; 1.80V nominal – VDD2 = 1.06–1.17V; 1.10V nominal VDDQ = 1.06 - 1.17V; 1.10V nominal or Low VDDQ = 0.57–0.65V; 0.60V nominal
Frequency range – 2133–10 MHz (data rate range: 4266–20 Mb/s/pin)
16n prefetch DDR architecture
8 internal banks per channel for concurrent operation
Single-data-rate CMD/ADR entry
Bidirectional/differential data strobe per byte lane
Programmable READ and WRITE latencies (RL/WL)
Programmable and on-the-fly burst lengths (BL = 16, 32)
Directed per-bank refresh for concurrent bank operation and ease of command scheduling
Up to 8.5 GB/s per die
On-chip temperature sensor to control self refresh rate
Partial-array self refresh (PASR)
Selectable output drive strength (DS)
Clock-stop capability
RoHS-compliant, “green” packaging
Programmable VSS (ODT) termination