TI SN74HC109NSR

These devices contain two independent J-K positive-edge-triggered flip-flops. A low level on the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data on the J and K̄ inputs that meets the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a specific voltage level and is not directly related to the rise time of the clock pulse. After the hold time interval, the data on the J and K̄ inputs can be changed without affecting the output levels. These versatile flip-flops can be operated as toggle flip-flops by tying K̄ low and J high. They can also function as D-type flip-flops by connecting J and K̄ together.