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TI CLVC1G175MDCKREP
| Manufacturer | |
| MPN | CLVC1G175MDCKREP |
| LCSC Part # | C2677778 |
| Packaging | SC-70-6 |
| Customer # | |
| Key Attributes | SINGLE D-TYPE FLIP-FLOP WITH ASYNCHRONOUS CLEAR |
| Datasheet |  TI CLVC1G175MDCKREP |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SC-70-6 | |
| Voltage - Supply | 1.65V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | - | |
| Operating Temperature | -55℃~+125℃ | |
| Series | 74LVC Series | |
| Synchronous/Asynchronous | Asynchronous | |
| Number of Elements | 1 | |
| Current - Output High(IOH) | 32mA | |
| Current - Output Low(IOL) | 32mA | |
| Setup Time | 1.5ns | |
| Quiescent Current | 10uA | |
| Hold Time | 700ps | |
| Propagation Delay | 5ns@5V,50pF | |
| Trigger Type | Rising Edge |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SC-70-6 | |
| Voltage - Supply | 1.65V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | - | |
| Operating Temperature | -55℃~+125℃ | |
| Series | 74LVC Series | |
| Synchronous/Asynchronous | Asynchronous |
| Type | Description | |
|---|---|---|
| Number of Elements | 1 | |
| Current - Output High(IOH) | 32mA | |
| Current - Output Low(IOL) | 32mA | |
| Setup Time | 1.5ns | |
| Quiescent Current | 10uA | |
| Hold Time | 700ps | |
| Propagation Delay | 5ns@5V,50pF | |
| Trigger Type | Rising Edge |
Introduction
This single D-type flip-flop is designed for 1.65-V to 5.5-V Vcc operation. The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR(overline) is high, data from the input pin (D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the low state, regardless of the clock edge or data on D. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Supports 5-V Vcc Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.3 ns at 3.3 V
- Low Power Consumption, 10 μA Max ICC
- ±24 mA Output Drive at 3.3 V
- Ioff Supports Partial Power-Down-Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 2.731 | $ 2.73 |
| 10+ | $ 2.6676 | $ 26.68 |
| 30+ | $ 2.6253 | $ 78.76 |
| 100+ | $ 2.5829 | $ 258.29 |
Standard Packaging3000/Full Reel | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SC-70-6 | |
| Voltage - Supply | 1.65V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | - | |
| Operating Temperature | -55℃~+125℃ | |
| Series | 74LVC Series | |
| Synchronous/Asynchronous | Asynchronous | |
| Number of Elements | 1 | |
| Current - Output High(IOH) | 32mA | |
| Current - Output Low(IOL) | 32mA | |
| Setup Time | 1.5ns | |
| Quiescent Current | 10uA | |
| Hold Time | 700ps | |
| Propagation Delay | 5ns@5V,50pF | |
| Trigger Type | Rising Edge |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | SC-70-6 | |
| Voltage - Supply | 1.65V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | - | |
| Operating Temperature | -55℃~+125℃ | |
| Series | 74LVC Series | |
| Synchronous/Asynchronous | Asynchronous |
| Type | Description | |
|---|---|---|
| Number of Elements | 1 | |
| Current - Output High(IOH) | 32mA | |
| Current - Output Low(IOL) | 32mA | |
| Setup Time | 1.5ns | |
| Quiescent Current | 10uA | |
| Hold Time | 700ps | |
| Propagation Delay | 5ns@5V,50pF | |
| Trigger Type | Rising Edge |
Introduction
This single D-type flip-flop is designed for 1.65-V to 5.5-V Vcc operation. The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR(overline) is high, data from the input pin (D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the low state, regardless of the clock edge or data on D. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Supports 5-V Vcc Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.3 ns at 3.3 V
- Low Power Consumption, 10 μA Max ICC
- ±24 mA Output Drive at 3.3 V
- Ioff Supports Partial Power-Down-Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
C2677778 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |