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TI SN74CB3T16210DGGR product image
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TI SN74CB3T16210DGGR

Manufacturer
MPN
SN74CB3T16210DGGR
LCSC Part #
C2674635
Packaging
TSSOP-48-6.1mm
Customer #
Key Attributes
20-BIT FET BUS SWITCH LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER
DatasheetTI SN74CB3T16210DGGR
RoHS Compliance1 documents available
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement
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QtyUnit PriceTotal Amount
1+$ 4.3545$ 4.35
10+$ 4.2445$ 42.45
30+$ 4.1706$ 125.12
100+$ 4.0951$ 409.51
Standard Packaging2000/Full Reel
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Signal Switches, Multiplexers, Decoders
ManufacturerTI
PackagingTSSOP-48-6.1mm
Type-
Number of Channels-
Voltage - Supply2.3V~3.6V
Operating Temperature-40℃~+85℃
Quiescent Current40uA
Current - Output High(IOH)-
Propagation Delay0.25ns@3.3V,50pF
FunctionPower-off protection;Output enable high-impedance;Level shifting
Current - Output Low(IOL)-

Introduction

AI Translation

The SN74CB3T16210 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (rₒₙ), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks V₍₍CC₎₎. The SN74CB3T16210 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels. The SN74CB3T16210 is organized as two 10-bit bus switches with separate output-enable (1OE̅, 2OE̅) inputs. It can be used as two 10-bit bus switches or as one 20-bit bus switch. When OE̅ is low, the associated 10-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 10-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Iₒff. The Iₒff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE̅ should be tied to V₍₍CC₎₎ through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Features

AI Translation
  • Member of the Widebus Family
  • Output Voltage Translation Tracks V₍₍CC₎₎
  • Supports Mixed-Mode Signal Operation on All Data I/O Ports
  • 5-V Input Down to 3.3-V Output Level Shift With 3.3-V V₍₍CC₎₎
  • 5-V/3.3-V Input Down to 2.5-V Output Level Shift With 2.5-V V₍₍CC₎₎
  • 5-V-Tolerant I/Os With Device Powered Up or Powered Down
  • Bidirectional Data Flow With Near-Zero Propagation Delay
  • Low ON-State Resistance (rₒₙ = 5 Ω Typ)
  • Low Input/Output Capacitance Minimizes Loading (Cᵢₒ₍₍OFF₎₎ = 5 pF Typ)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (I₍₍CC₎₎ = 40 μA Max)
  • V₍₍CC₎₎ Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Iₒff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

Applications

AI Translation
  • Level Translation
  • PCI Interface
  • USB Interface
  • Memory Interleaving
  • Bus Isolation
  • Low-Power Portable Equipment