TI CD74HC147PWR

The ’HC147 and CD74HCT147 are high speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL). The ’HC147 and CD74HCT147 9-input priority encoders accept data from nine active LOW inputs (l₀ to l₉) and provide binary representation on the four active LOW inputs Y₀(overline) to Y₃). A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line l₉ having the highest priority. These devices provide the 10-line to 4-line priority encoding function by use of the implied decimal “zero”. The “zero” is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH.

• Buffered Inputs and Outputs
• Typical Propagation Delay: 13ns at Vcc = 5V, CL = 15pF, TA = 25℃
• Fanout (Over Temperature Range)
  • Standard Outputs: 10 LSTTL Loads
  • Bus Driver Outputs: 15 LSTTL Loads
• Wide Operating Temperature Range: -55℃ to 125℃
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
  • 2V to 6V Operation
  • High Noise Immunity: NIL = 30%, N₁ₕ = 30% of Vcc at Vcc = 5V
• HCT Types
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, Vₗ = 0.8V (Max), Vₕ = 2V (Min)
  • CMOS Input Compatibility, I ≤ 1μA at Voₗ, Voₕ