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TI DS91M040TSQX/NOPB product image
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TI DS91M040TSQX/NOPBRoHS

Manufacturer
MPN
DS91M040TSQX/NOPB
LCSC Part #
C2672371
Packaging
WQFN-32-EP(5x5)
Customer #
Key Attributes
DS91M040 125 MHz Quad M-LVDS Transceiver
Datasheetpdf iconTI DS91M040TSQX/NOPB
In-Stock: 342
342 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 10.0161$ 10.02
10+$ 8.7659$ 87.66
30+$ 8.0054$ 240.16
100+$ 7.3666$ 736.66
Standard Packaging4500/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Interface/Drivers, Receivers, Transceivers
ManufacturerTI
PackagingWQFN-32-EP(5x5)
Voltage - Supply3V~3.6V
TypeTransceiver
Data Rate250Mbps
Operating Temperature-40℃~+85℃
Number of Drivers4
FeaturesFail-safe;Edge rate control
Level StandardLVDS
Number of Receivers4

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging4500
Sales UnitPiece

Introduction

AI Translation

The DS91M040 is a quad M- LVDS transceiver designed for driving / receiving clock or data signals to / from up to four multipoint networks.

M- LVDS (Multipoint LVDS) is a new family of bus interface devices based on LVDS technology specifically designed for multipoint and multidrop cable and backplane applications. It differs from standard LVDS in providing increased drive current to handle double terminations that are required in multipoint applications. Controlled transition times minimize reflections that are common in multipoint configurations due to unterminated stubs. M- LVDS devices also have a very large input common mode voltage range for additional noise margin in heavily loaded and noisy backplane environments.

A single DS91M040 channel is a half- duplex transceiver that accepts LVTTL/LVCMOS signals at the driver inputs and converts them to differential M- LVDS signal levels. The receiver inputs accept low voltage differential signals (LVDS, BLVDS, M- LVDS, LVPECL and CML) and convert them to 3V LVCMOS signals. The DS91M040 supports both M- LVDS type 1 and type 2 receiver inputs.

Features

AI Translation
  • DC - 125 MHz / 250 Mbps Low Jitter, Low Skew, Low Power Operation
  • Wide Input Common Mode Voltage Range Allows up to ± 1V of GND Noise
  • Conforms to TIA/EIA- 899 M- LVDS Standard
  • Pin Selectable M- LVDS Receiver Type (1 or 2)
  • Controlled Transition Times (2.0 ns typ) Minimize Reflections
  • 8 kV ESD on M- LVDS I/O pins protects adjoining components
  • Flow- Through Pinout Simplifies PCB Layout
  • Small 5 mm x 5 mm WQFN- 32 Space Saving Package

Applications

AI Translation
  • Multidrop / Multipoint Clock and Data Distribution
  • High- Speed, Low Power, Short- Reach Alternative to TIA/EIA- 465/422
  • Clock Distribution in AdvancedTCA (ATCA) and MicroTCA (uTCA, uTCA) Backplanes