TI ADC32J24IRGZT

The ADC32J2x family are high-linearity, ultra-low-power, dual-channel, 12-bit, 50MSPS to 160MSPS ADCs. These devices are specifically designed to support demanding high-input-frequency signals with wide dynamic range requirements. A clock input divider provides greater flexibility in system clock architecture design, and the SYSREF input enables system-wide synchronization. The devices support the JESD204B interface, reducing the number of interface lines and achieving high system integration. The JESD204B interface is a serial interface that serializes each ADC's data output over a single differential pair. An internal PLL multiplies the incoming ADC sample clock by 20 to generate the bit clock used for serializing 12-bit data per channel. The devices support Subclass 1 with interface rates up to 3.2Gbps.

• Dual-channel
• 12-bit resolution
• 1.8V single supply
• Flexible input clock buffer supporting 1×, 2×, and 4× division
• At f₁ₙ = 70MHz: SNR = 70.3dBFS, SFDR = 88dBc
• Ultra-low power: 227mW per channel at 160MSPS
• Channel isolation: 105dB
• Internal dither
• JESD204B serial interface: compatible with subclass 0, 1, 2, up to 3.2Gbps
• One lane per ADC (up to 160MSPS)
• Multi-chip synchronization support
• Pin-to-pin compatible with 14-bit version (ADC32J4X)
• Package: VQFN-48 (7mm × 7mm)

• Multi-carrier, multi-mode cellular base stations
• Network and vector analyzers
• Communications test equipment
• Non-destructive testing
• Microwave receivers
• SDR quadrature and diversity radio receivers
• Motor control feedback