SILICON LABS SI5397C-A-GMR

The Si5397 is a high-performance, 8-output jitter-attenuating clock multiplier which integrates four any-frequency DSPLLs for applications that require maximum integration and independent timing paths. The Si5396 is a dual DSPLL version with either 4 outputs or 12 outputs. Each DSPLL has access to any of the four inputs and can provide low jitter clocks on any of the device outputs. Device grades J/K/L/M have an integrated reference to save board space, improve system reliability and reduces the effect of acoustic emissions noise caused by temperature ramps. Grades A/B/C/D use an external crystal (XTAL) or crystal oscillator (XO) reference. Based on 4th generation DSPLL technology, these devices provide any-frequency conversion with typical jitter performance of 95 fs. Each DSPLL supports independent free-run, holdover modes of operation, as well as automatic and hitless input clock switching. The Si5397/96 is programmable via a serial interface with in-circuit programmable non-volatile memory so that it always powers up in a known configuration. Programming the Si5397/96 is easy with Silicon Labs' ClockBuilderTM Pro software. Factory pre-programmed devices are also available.

• Each DSPLL generates any output frequency from any input frequency
• Four or two DSPLLs to synchronize to multiple time domains
• Ultra-low phase jitter of 95 fs rms
• Enhanced hitless switching minimizes output phase transients
• Input frequency range:
  • Differential: 8 kHz to 750 MHz
  • LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
  • Differential: 100 Hz to 720 MHz
  • LVCMOS: 100 Hz to 250 MHz
• Status Monitoring
• External reference: Grades A/B/C/D
• Integrated reference: Grades J/K/L/M
• Drop-in compatible with Si5347/46
• Generates any output frequency in any format from any input frequency
• External XTAL or XO reference (A/B/C/D)
• Integrated reference (J/K/L/M)
• Four or two DSPLLs to synchronize to multiple inputs
• Flexible crosspoints route any input to any output clock
• Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz to 4 kHz
• Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal amplitude
• Status monitoring (LOS, OOF, LOL)
• Enhanced hitless switching minimizes output phase transients for 8 kHz, 19.44 MHz, 25 MHz, and other input frequencies
• Locks to gapped clock inputs
• Automatic free-run and holdover modes
• Fastlock feature for low nominal bandwidths
• Independent Frequency-on-the-fly for each DSPLL
• DCO mode: as low as 0.01 ppb steps per DSPLL
• Core voltage:
  • VDD: 1.8V ±5%
  • VDDA: 3.3V ±5%
• Independent output clock supply pins: 3.3, 2.5, or 1.8 V
• Serial interface: I2C or SPI
• In-circuit programmable with non-volatile OTP memory
• ClockBuilder Pro software tool simplifies device configuration
• Temperature range: –40 to +85 ℃
• Pb-free, RoHS-6 compliant

• OTN Muxponders and Transponders
• 10/40/100/400GbE
• Synchronous Ethernet (ITU-T G.8262)
• 10/25/100G Carrier Ethernet switches
• Broadcast video