SILICON LABS SI5344H-C05857-GMR

This specialized jitter attenuating clock multiplier combines fourth-generation DSPLL with ultra-low phase jitter and MultiSynth technologies to enable high data rate coherent optical transceiver design. Up to four outputs can be assigned to High Frequency Mode capable of up to 2.75 GHz at 50 fs-rms typical phase jitter (1 MHz - 40 MHz). Each output may also be configured as MultiSynth Mode any-frequency outputs when added frequency flexibility is required, such as clocking Forward Error Correction (FEC) while still delivering < 150 fs-rms typical phase jitter (12 kHz - 20 MHz). The Si5344H and Si5342H also feature DCO control with as low as 0.001 ppb step control and locks to gapped clock inputs. These devices are programmable via a serial interface with in-circuit programmable non-volatile memory (NVM) so that they always power up with a known frequency configuration. The loop filter is fully integrated on-chip eliminating the risk of potential noise coupling associated with discrete solutions. Programming the Si5342H/44H is made easy with Silicon Labs’ ClockBuilder Pro software. Factory preprogrammed devices are also available.

• High-speed outputs generate an ultra-low jitter output up to 2.75 GHz
• Up to four Multi-Synth outputs generate any frequency up to 717.5 MHz
• Input frequency range: 8 kHz to 750 MHz
• Maximum Output frequency:
  • High-Frequency Mode: 2.75 GHz
  • MultiSynth Mode: 717.5 MHz
• Jitter performance:
  • High Frequency Mode: < 50 fs typ (1 MHz–40 MHz)
  • MultiSynth Mode: < 150 fs typ (12 kHz - 20 MHz)
• Programmable jitter attenuation bandwidth: 10 Hz to 4 kHz
• Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable voltage swing and common mode (LVPECL-only in High Frequency Mode)
• Status monitoring (LOS, OOF, LOL)
• Hitless input clock switching: automatic or manual
• Automatic free-run and holdover modes
• Glitchless on the fly output frequency changes
• Locks to gapped clock inputs
• DCO mode: as low as 0.001 ppb steps
• Core voltage:
  • VDD: 1.8 V ±5%
  • VDDA: 3.3 V ±5%
• Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V
• Serial interface: I²C or SPI
• In-circuit programmable with non-volatile OTP memory
• ClockBuilder Pro software simplifies device configuration
• Temperature range: –40 to +85 ℃
• Pb-free, RoHS-6 compliant

• 100G/200G/400G Optical
• Wireless base-stations
• Transceivers