SILICON LABS SI5384A-D07173-GMR

The Si5383/84 combines the industry’s smallest footprint and lowest power network synchronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The Si5383/84 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless communications systems, and data center switches requiring both traditional and packet based network synchronization. The three independent DSPLLs are individually configurable as a SyncE PLL, IEEE 1588 DCO, or a general-purpose PLL for processor/FPGA clocking. The Si5383/84 can also be used in legacy SETS systems needing Stratum 3/3E compliance. In addition, locking to a 1 PPS input frequency is available on DSPLL D. The DCO mode provides precise timing adjustment to 1 part per trillion (ppt). The unique design of the Si5383/84 allows the device to accept a TCXO/OCXO reference with a wide frequency range, and the reference clock jitter does not degrade the output performance. The Si5383/84 is configurable via a serial interface and programming the Si5383/84 is easy with ClockBuilder Pro software. Factory pre-programmed devices are also available.

• One or three independent DSPLLs in a single monolithic IC supporting flexible SyncE/IEEE 1588 and SETS architectures
• Input frequency range:
  • External crystal: 25 - 54 MHz
  • REF clock: 5 - 250 MHz
  • Diff clock: 8 kHz - 750 MHz
  • LVCMOS clock: 1 PPS, 8 kHz - 250 MHz
• Output frequency range:
  • Differential: 1 PPS, 100 Hz - 718.5 MHz
  • LVCMOS: 1 PPS, 100 Hz - 250 MHz
• Ultra-low jitter of less than 150 fs
• Meets the requirements of:
  • ITU-T G.8273.1 T-GM
  • ITU-T G.8273.2 T-BC, T-TSC
  • Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Options 1 and 2
  • ITU-T G.812 Type III, IV
  • ITU-T G.813 Option 1
  • Telcordia GR-1244, GR-253 (Stratum-3/3E)
• Each DSPLL generates any output frequency from any input frequency
• Pin or software controllable DCO on each DSPLL with typical resolution to 1 ppt/step
• TCXO/OCXO reference input determines DSPLL free-run/holdover accuracy and stability
• Excellent jitter performance
• Programmable loop bandwidth per DSPLL:
  • 1 PPS inputs: 1 mHz and 10 mHz
  • All other inputs: 1 mHz to 4 kHz
• Highly configurable output drivers: LVDS, LVPECL, LVCMOS, HCSL, CML
• Core voltage:
  • VDD: 1.8 ± 5%
  • VDDA: 3.3 ± 5%
• Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V
• Built-in power supply filtering
• Status monitoring:
  • LOS, LOL: 1 PPS - 750 MHz
  • OOF: 8 kHz - 750 MHz
• I2C Serial Interface
• ClockBuilder Pro software tool simplifies device configuration
• 5 input, 7 output, 56-pin LGA
• Temperature range: -40 to +85 ℃
• Pb-free, RoHS-6 compliant

• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Options 1 and 2
• Telecom Grand Master Clock (T-GM) as defined by ITU-T G.8273.1
• Telecom Boundary Clock and Slave Clock (T-BC, T-TSC) as defined by ITU-T G. 8273.2
• IEEE 1588 (PTP) slave clock synchronization
• Stratum 3/3E, G.812, G.813, GR-1244, GR-253 network synchronization
• Hz/PPS Clock Multiplier