TI SN74SSTVF16859S8G3

This is a 13-bit to 26-bit registered buffer designed for VCC operating voltages of 2.3 V to 2.7 V. All inputs are SSTL_2 type, except for the LVCMOS reset (RESET) input. All outputs are edge-rate-controlled LVCMOS circuits, optimized for unterminated DIMM loads. The SN74SSTVF16859 operates with differential clocks (CLK and CLK), with data latched at the crossing point of the CLK rising edge and CLK falling edge. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, allowing undriven (floating) data, clock, and reference voltage VREF inputs; in addition, all registers are reset and all outputs are forced low. The LVCMOS RESET input must always be held at a valid logic-high or logic-low level. To ensure the register outputs are in a defined state before a stable clock is supplied, RESET must be held low during power-up. The center die pad of the RGQ package must be connected to GND.

• PC1600, PC2100, and PC2700 operating voltage range: 2.3 V to 2.7 V
• PC3200 (QFN package) operating voltage range: 2.5 V to 2.7 V
• 600 ps faster than JEDEC standard SSTV16859 in PC2700 DIMM simultaneous switching applications
• 1-to-2 output, stacked DDR DIMM support
• Output edge-rate control circuitry minimizes switching noise on unterminated lines
• Outputs compliant with SSTL_2 Class I specification
• SSTL_2 data input support
• Differential clock (CLK and CLK) inputs
• RESET input supports LVCMOS switching levels
• RESET input disables differential input receivers, resets all registers, and forces all outputs low
• Pin arrangement optimized for DIMM PCB routing
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• ESD protection exceeds JESD 22: 2000-V Human Body Model (A114-A); 200-V Machine Model (A115-A); 1000-V Charged Device Model (C101)

• PC2700 DIMM
• Stacked DDR DIMM