ROHM BR25H080FVT-2CE2

BR25H080-2C is a serial EEPROM of SPI BUS interface method.

• High speed clock action up to 10MHz (Max.)
• Wait function by HOLDB terminal.
• Part or whole of memory arrays settable as read only memory area by program.
• 2.5V to 5.5V single power source action most suitable for battery use.
• Page write mode useful for initial value write at factory shipment.
• For SPI bus interface (CPOL, CPHA)=(0, 0), (1, 1)
• Self-timed programming cycle.
• Low Supply Current At write operation (5V) : 1.0mA (Typ.) At read operation (5V) : 1.0mA (Typ.) At standby operation (5V) : 0.1μA (Typ.)
• Address auto increment function at read operation
• Prevention of time mistake
• Write prohibition at power on.
• Write prohibition by command code (WRDI).
• Write prohibition by WPB pin.
• Write prohibition block setting by status registers (BP1, BP0).
• Prevention of write mistake at low voltage.
• MSOP8, TSSOP-B8, SOP8, SOP-J8 Package
• Data at shipment Memory array: FFh, status register WPEN, BP0:0
• More than 100 years data retention.
• More than 1 million write cycles.
• AEC-Q100 Qualified.
• This IC has status registers. The status registers are of 8 bits and express the following parameters. BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are valid even when power source is turned off.
• Number of data rewrite times and data hold time are same as characteristics of the EEPROM.
• WEN can be set by write enable command and write disable command. WEN becomes write disable status when power source is turned off. R/B is for write confirmation, therefore cannot be set externally.
• The value of status register can be read by read status command.
• By setting WPB = LOW, write command is prohibited. As for BR25H080-2C, only when WPEN bit is set “1”, the WPB pin functions become valid. And the write command to be disabled at this moment is WRSR. However, when write cycle is in execution, no interruption can be made.
• By HOLDB pin, data transfer can be interrupted. When SCK = 0, by making HOLDB from “1” into “0”, data transfer to EEPROM is interrupted. When SCK = 0, by making HOLDB from “0” into “1”, data transfer is restarted.