micron AS4C512M8D3-12BCNTR

The 4Gb DDR3 DRAM employs a double data rate architecture for high-speed operation, with an internal configuration of 8 banks. The 4Gb device is organized as 64Mb x 8 I/O x 8 banks. These synchronous devices support high-speed DDR transfers of up to 1600 Mb/s/pin in general applications. The device is designed to comply with all key DDR3 DRAM features; all control and address inputs are synchronized to a pair of externally supplied differential clocks. Inputs are latched at the crossing point of the differential clock (CK rising and CK# falling). All I/Os are source-synchronous, referenced to a differential DQS pair. These devices operate from a single 1.5V ± 0.075V supply and are available in a BGA package.

• JEDEC compliant
• Supply voltage: VDD and VDDQ = +1.5V ± 0.075V
• Operating temperature: Commercial (Extended) (0 ~ 95°C); Industrial (-40 ~ 95°C)
• JEDEC clock jitter specification support
• Fully synchronous operation
• Fast clock rate: 800MHz
• Differential clock, CK and CK#
• Bidirectional differential data strobe — DQS and DQS#
• 8 internal banks for concurrent operation
• 8n-bit prefetch architecture
• Internal pipelined architecture
• Precharge and active power-down
• Programmable mode and extended mode registers
• Additive Latency (AL): 0, CL - 1, CL - 2
• Programmable burst length: 4, 8
• Burst type: Sequential/Interleaved
• Output driver impedance control
• 8192 refresh cycles per 64ms
• Average refresh period: 7.8μs (-40°C ≤ TC ≤ +85°C); 3.9μs (+85°C < TC ≤ +95°C)
• Write leveling
• OCD calibration
• Dynamic ODT (Rtt_Nom and Rtt_WR)
• RoHS compliant
• Auto refresh and self-refresh
• 78-ball 9×10.5×1.2mm FBGA package
• All components RoHS compliant