ISSI IS42S81600D-6TL-TR

ISSI's 128Mb SDRAM uses a pipelined architecture to achieve high-speed data transfer. All input and output signals are referenced to the rising edge of the clock input. The 128Mb SDRAM is organized as follows: it is a high-speed CMOS DRAM designed for memory systems operating at 3.3V VDD and 3.3V VDDQ, containing 134,217,728 bits. It is internally configured as a four-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows × 512 columns × 16 bits or 4,096 rows × 1,024 columns × 8 bits. The SDRAM includes an auto-refresh mode and a power-saving power-down mode. All signals are registered on the positive edge of clock signal CLK. All inputs and outputs are LVTTL-compatible. It supports synchronous burst data transfer at high data rates with automatic column address generation, interleaving between internal banks to hide precharge time, and random column address changes at every clock cycle during burst access. With auto-precharge enabled, a self-timed row precharge can be initiated at the end of a burst sequence. Precharging one bank while accessing one of the other three banks hides the precharge cycle and provides seamless, high-speed, random access operation. SDRAM read and write accesses are burst-oriented, starting from a selected location and continuing for a programmed number of locations in a programmed sequence. A registered ACTIVE command initiates access, followed by a READ or WRITE command. The ACTIVE command is used with registered address bits to select the bank and row to be accessed (BA0 and BA1 select the bank; A0–A11 select the row). The READ or WRITE command is used with registered address bits to select the starting column location for the burst access. Programmable read or write burst lengths include 1, 2, 4, and 8 locations or full page, with a burst terminate option.

• Clock frequency: 166, 143, 133 MHz
• Fully synchronous; all signals referenced to positive clock edge
• Internal banks for hidden row access/precharge
• Power supply: LVTTL interface
• Programmable burst length – (1, 2, 4, 8, full page)
• Programmable burst sequence: sequential/interleaved
• Auto refresh (CBR)
• Self-refresh with programmable refresh period
• 4096 refresh cycles per 64 ms
• Random column address every clock cycle
• Programmable C̄Ā̄S̄ latency (2, 3 clocks)
• Burst read/write and burst read/single write operation capability
• Burst termination via burst stop and precharge commands
• Industrial temperature available
• Lead-free available