ISSI IS42S16100C1-6T

ISSI's 16Mb synchronous DRAM IS42S16100C1 is organized as 524,288 words x 16 bits x 2 banks for enhanced performance. The SDRAM employs a pipelined architecture to achieve high-speed data transfer. All input and output signals are referenced to the rising edge of the clock input.

• Clock frequencies: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to positive clock edge
• Two banks operable simultaneously and independently
• Dual internal banks controlled by A11 (bank select)
• Single 3.3V supply, LVTTL interface
• Programmable burst length — (1, 2, 4, 8, full page)
• Programmable burst sequence: sequential/interleaved
• 4096 refresh cycles per 64 ms
• Random column address every clock cycle
• Programmable CAS̄ latency (2, 3 clocks)
• Burst read/write and burst read/single write capable
• Burst termination via burst stop and precharge commands
• Byte control by LDQM and UDQM
• Up to 143 MHz at industrial temperature
• Package: 400-mil 50-pin TSOP-II, 60-ball fBGA
• Lead-free package option available