TI DRA821U4TCBALMRQ1

The Jacinto DRA821x processor is based on the ARMv8 64-bit architecture, optimized for gateway systems with cloud connectivity. The SoC design reduces system-level cost and complexity through integration, particularly by integrating a system MCU, functional safety and security features, and an Ethernet switch for high-speed communications. The integrated diagnostics and functional safety features meet ASIL-D and SIL 3 certification requirements. The PCIe controller and TSN-capable Gigabit Ethernet switch enable real-time control and low-latency communications.

Up to four general-purpose Arm Cortex-R5F subsystems can handle low-level, time-critical processing tasks, allowing Arm Cortex-A72 cores to run high-level and cloud-based applications without interference.

The Jacinto DRA821x processor also introduces the concept of an extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain, designed to achieve higher functional safety such as ASIL-D/SIL-3. The functional block diagram highlights the IPs included in the eMCU. For more details on the eMCU and functional safety, refer to the Texas Instruments Jacinto 7 Family DRA821 Safety Manual (SPRUIX4).

• Processor Cores:
  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem, up to 2.0 GHz, 24K DMIPS
    • 1MB L2 shared cache per dual-core Cortex-A72 cluster
    • 32KB L1 data cache and 48KB L1 instruction cache per A72 core
  • 4× Arm Cortex-R5F MCU, up to 1.0 GHz, optional lockstep operation, 8K DMIPS
    • 32K instruction cache, 32K data cache, 64K L2 tightly coupled memory (TCM)
    • 2× Arm Cortex-R5F MCU in isolated MCU subsystem
    • 2× Arm Cortex-R5F MCU in general-purpose compute partition
• Memory Subsystem:
  • 1MB on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherency cache
    • Internal DMA engine support
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory type per JESD209-4B (byte-mode LPDDR4 and memories with row address bits exceeding 17 not supported)
    • Up to 3200 MT/s
    • 32-bit and 16-bit data bus, inline ECC bus up to 12.8 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in main domain, ECC-protected
• Virtualization:
  • Arm Cortex-A72 hypervisor support
    • Dedicated processing subsystem including Arm Cortex-A72 and Arm Cortex-R5F with isolated safety MCU island
  • IO virtualization support
    • Peripheral Virtualization Unit (PVU) for low-latency, high-bandwidth peripheral traffic
  • Multi-region firewall support for memory and peripheral isolation
  • Virtualization support for Ethernet, PCIe, and DMA
• Device Security (select variants):
  • Secure boot and secure runtime support
  • Customer-programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Cryptographic hardware accelerator – PKA with ECC, AES, SHA, RNG, DES, and 3DES
• Functional Safety:
  • Select variants comply with functional safety standards
    • Developed for functional safety applications
    • Documentation provided to support ISO 26262 and IEC 61508 functional safety system design, targeting ASIL-D/SIL-3
    • System capability target: ASIL-D/SIL-3
    • Hardware integrity target for MCU domain: ASIL-D/SIL-3
    • Hardware integrity target for main domain extended MCU (EMCU) portion: ASIL-D/SIL-3
    • Hardware integrity target for remainder of main domain: ASIL-B/SIL-2
    • FFI isolation between EMCU and remainder of main domain
    • Safety-related certification • ISO 26262 and IEC 61508 certification planned
    • Variants ending in Q1 comply with AEC-Q100
• High-Speed Interfaces:
  • Integrated Ethernet TSN/AVB switch with up to 4 (DRA821U4) or 2 (DRA821U2) external ports
    • One port supports 5Gb, 10Gb USXGMII/XFI
    • All ports support 2.5Gb SGMII
    • All ports support 1Gb SGMII/RGMII
    • DRA821U4: any single port can support QSGMII (using all 4 internal ports)
    • Non-blocking wire-speed store-and-forward switch
    • InterVLAN (Layer 3) routing support
    • IEEE 1588 (Annex D, E, F) time synchronization support
    • TSN/AVB traffic scheduling and shaping support
    • Port mirroring for debug and diagnostics
    • Traffic policing and rate limiting support
  • One RGMII/RMII port in safety MCU island
  • One PCI-Express Gen3 controller
    • Gen1, Gen2, and Gen3 operation with auto-negotiation
    • 4-lane
  • One USB 3.1 Gen1 dual-role device subsystem
    • Type-C switching support
    • Independently configurable as USB host, USB peripheral, or USB dual-role device
• Automotive Interfaces:
  • 20× CAN-FD ports
  • 12× UART
  • 11× SPI
  • One 8-channel ADC
  • 10× I2C
  • 2× I3C
• Audio Interfaces:
  • 3× multichannel audio serial port (McASP) modules
• Flash Interfaces:
  • Embedded MultiMediaCard (eMMC 5.1) interface
    • Up to HS400 speed
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interface
  • One octal SPI / Xccela / HyperBus memory controller (HBMC) interface
• 16nm FinFET process technology
• 17.2 mm × 17.2 mm package, 0.8 mm pitch, IPC Class 3 PCB compliant

• Automotive Gateway
• Vehicle Computing
• Body Control Module
• Telematics Control Unit
• V2X/V2V
• Factory Automation Gateway
• Communication Equipment
• Industrial Transportation
• Building Automation Gateway