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EDA 모델EasyEDA
TI AM2431BSDGHIALXR
| 제조업체 | |
| 제조사 품번 | AM2431BSDGHIALXR |
| LCSC 번호 | C20345195 |
| 포장 | FCCSP-293 |
| 고객 번호 | |
| 주요 제원 | Sitara microcontroller |
| 데이터시트 | TI AM2431BSDGHIALXR |
| RoHS 준수 | 2개 문서 이용 가능 |
제품 사양
전체
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| 제조업체 | TI | |
| 포장 | FCCSP-293 | |
| Number of I/O | 148 | |
| Operating Temperature | -40℃~+125℃@(TJ) | |
| Voltage - Supply | 1.71V~1.89V;3.135V~3.465V | |
| EEPROM | - | |
| CPU Core | ARM Cortex-M4F;ARM Cortex-R5F | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 400MHz;800MHz | |
| Oscillator Type | Built-in+External |
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| 제조업체 | TI | |
| 포장 | FCCSP-293 | |
| Number of I/O | 148 | |
| Operating Temperature | -40℃~+125℃@(TJ) | |
| Voltage - Supply | 1.71V~1.89V;3.135V~3.465V |
| 타입 | 설명 | |
|---|---|---|
| EEPROM | - | |
| CPU Core | ARM Cortex-M4F;ARM Cortex-R5F | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 400MHz;800MHz | |
| Oscillator Type | Built-in+External |
도움말 및 피드백유사 제품 보기 (0) >
주요 특징
AI 번역
- Processor cores:
- Up to 2 x Dual-core Arm Cortex-R5F MCU subsystems operating at up to 800 MHz, highly-integrated for real-time processing
- Dual-core Arm Cortex-R5F clusters support dual-core and single-core operation
- 32KB ICache and 32KB DCache per R5F core with SECDED ECC on all memories
- Single-core: 128KB TCM per cluster (128KB TCM per R5F core)
- Dual-core: 128KB TCM per cluster (64KB TCM per R5F core)
- 1 x Single-core Arm Cortex-M4F MCU at up to 400 MHz
- 256KB SRAM with SECDED ECC
- Memory subsystem:
- Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC: Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks. Each memory bank can be allocated to a single core to facilitate software task partitioning
- DDR Subsystem (DDRSS): Supports LPDDR4, DDR4 memory types. 16-Bit data bus with inline ECC. Supports speeds up to 1600 MT/s
- System on Chip (SoC) services:
- Device Management Security Controller (DMSC-L): Centralized SoC system controller. Manages system services including initial boot, security, and clock/reset/power management. Communication with various processing units over message manager. Simplified interface for optimizing unused peripherals. On-Chip Debug functionality through JTAG and Trace interfaces
- Data Movement Subsystem (DMSS): Block Copy DMA (BCDMA), Packet DMA (PKTDMA), Secure Proxy (SEC_PROXY), Ring Accelerator (RINGACC)
- Time Sync Subsystem: Central Platform Time Sync (CPTS) module, Timer Manager (TIMERMANAGER) with 1024 timers, Time Sync and Compare event interrupt routers
- Industrial subsystem:
- 2x Gigabit Industrial Communication Subsystems (PRU_ICSSG): Optional support for Profinet (RT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and other Networking Protocols. Backwards compatibility with 10/100Mb PRU_ICSS
- Each PRU_ICSSG contains 3x PRU RISC Cores per Slice (2x Slice per PRU_ICSSG): PRU General Use core (PRU), PRU Real-Time Unit core (PRU-RTU), PRU Transmit core (PRU-TX)
- Each PRU core supports: Instruction RAM with ECC, Broadside RAM Multiplier with optional accumulator (MAC), CRC16/32 hardware accelerator, Byte swap for Big/Little Endian conversion, SUM32 hardware accelerator for UDP checksum, Task Manager for preemption support
- Up to 2x Ethernet ports: RGMII (10/100/1000), MII (10/100)
- Three Data RAMs with ECC, 8 banks of 30 x 32-bit register scratchpad memory
- Interrupt controller and task manager
- 2 x 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
- 18x Sigma-Delta Filter Module (SDFM) interfaces
- Short circuit logic
- Over-current logic
- 6x Multi-protocol position encoder interfaces
- 1 x Enhanced Capture Module (ECAP)
- 16550-compatible UART
- Dedicated 192-MHz clock to support 12-Mbps PROFIBUS
- Security:
- Secure Boot supported
- Hardware-enforced Root-of-Trust (RoT)
- Support to switch RoT via backup key
- Support for takeover protection, IP protection, and anti-roll back protection
- Support for cryptographic acceleration
- Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
- DMA support
- Supports cryptographic cores: AES - 128/192/256-bit key sizes, 3DES - 56/112/168-bit key sizes, MD5, SHA1, SHA2 - 224/256/384/512-bit key sizes, DRBG with true random number generator, PKA (Public Key Accelerator) to Assist in RSA/ECC processing
- Debugging security: Secure software-controlled debug access, Security aware debugging
- Secure storage support
- On-the-Fly encryption (OTFE) support for OSPI in XIP mode
- Networking security support for data (Payload) encryption/authentication via packet-based hardware cryptographic engine
- DMSC-L co-processor for security and key management, with dedicated device level interconnect
- General connectivity peripherals:
- 6x Inter-Integrated Circuit (I2C) ports
- 9x configurable Universal Asynchronous Receive/ Transmit (UART) modules
- 1 x 12-bit Analog-to-Digital Converters (ADC): Configurable sample rate up to 4 MSPS, 8x multiplexed analog inputs
- 7x Multichannel Serial Peripheral Interfaces (SPI) controllers
- 3x General-Purpose I/O (GPIO) modules
- Industrial and control interfaces:
- 9x Enhanced Pulse-Width Modulator (EPWM) modules
- 3x Enhanced Capture (ECAP) modules
- 3x Enhanced Quadrature Encoder Pulse (EQEP) modules
- 2x Modular Controller Area Network (MCAN) modules with full CAN-FD support
- 2x Fast Serial Interface Transmitter (FSITX) cores
- 6x Fast Serial Interface Receiver (FSIRX) cores
- High-speed interfaces:
- 1 x Integrated Ethernet switch supporting up to 2 external ports (CPSW3G): Up to 2 Ethernet ports, RGMII (10/100/1000), RMII (10/100), IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP, Clause 45 MDIO PHY management, Energy efficient Ethernet (802.3rd)
- 1 x PCI-Express Gen2 controller (PCIE): Supports Gen2 Single Lane operation
- 1 x USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS): Port configurable as USB host, USB device, or USB Dual-Role device. USB device: High-speed (480 Mbps) and Full-speed (12 Mbps). USB host: SuperSpeed Gen 1 (5 Gbps), High-speed (480 Mbps), Full-speed (12 Mbps), and Low-speed (1.5 Mbps). Integrated USB VBUS detection
- 1 x Serializer/Deserializer (SERDES): One SerDes PHY lane to support either PCI-Express Gen2 or USB Super-Speed Gen1
- Media and data storage:
- 2x MultiMedia Card/Secure Digital (MMCSD) interfaces: One 8-bit for eMMC (MMCSD0), One 4-bit for SD/SDIO (MMCSD1). Integrated analog switch for voltage switching between 3.3V to 1.8V for high-speed card
모든 주문 보장
100% 정품 · 30일 반품 또는 교환
제품 사양
전체
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| 제조업체 | TI | |
| 포장 | FCCSP-293 | |
| Number of I/O | 148 | |
| Operating Temperature | -40℃~+125℃@(TJ) | |
| Voltage - Supply | 1.71V~1.89V;3.135V~3.465V | |
| EEPROM | - | |
| CPU Core | ARM Cortex-M4F;ARM Cortex-R5F | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 400MHz;800MHz | |
| Oscillator Type | Built-in+External |
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| 제조업체 | TI | |
| 포장 | FCCSP-293 | |
| Number of I/O | 148 | |
| Operating Temperature | -40℃~+125℃@(TJ) | |
| Voltage - Supply | 1.71V~1.89V;3.135V~3.465V |
| 타입 | 설명 | |
|---|---|---|
| EEPROM | - | |
| CPU Core | ARM Cortex-M4F;ARM Cortex-R5F | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 400MHz;800MHz | |
| Oscillator Type | Built-in+External |
도움말 및 피드백유사 제품 보기 (0) >
주요 특징
AI 번역
- Processor cores:
- Up to 2 x Dual-core Arm Cortex-R5F MCU subsystems operating at up to 800 MHz, highly-integrated for real-time processing
- Dual-core Arm Cortex-R5F clusters support dual-core and single-core operation
- 32KB ICache and 32KB DCache per R5F core with SECDED ECC on all memories
- Single-core: 128KB TCM per cluster (128KB TCM per R5F core)
- Dual-core: 128KB TCM per cluster (64KB TCM per R5F core)
- 1 x Single-core Arm Cortex-M4F MCU at up to 400 MHz
- 256KB SRAM with SECDED ECC
- Memory subsystem:
- Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC: Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks. Each memory bank can be allocated to a single core to facilitate software task partitioning
- DDR Subsystem (DDRSS): Supports LPDDR4, DDR4 memory types. 16-Bit data bus with inline ECC. Supports speeds up to 1600 MT/s
- System on Chip (SoC) services:
- Device Management Security Controller (DMSC-L): Centralized SoC system controller. Manages system services including initial boot, security, and clock/reset/power management. Communication with various processing units over message manager. Simplified interface for optimizing unused peripherals. On-Chip Debug functionality through JTAG and Trace interfaces
- Data Movement Subsystem (DMSS): Block Copy DMA (BCDMA), Packet DMA (PKTDMA), Secure Proxy (SEC_PROXY), Ring Accelerator (RINGACC)
- Time Sync Subsystem: Central Platform Time Sync (CPTS) module, Timer Manager (TIMERMANAGER) with 1024 timers, Time Sync and Compare event interrupt routers
- Industrial subsystem:
- 2x Gigabit Industrial Communication Subsystems (PRU_ICSSG): Optional support for Profinet (RT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and other Networking Protocols. Backwards compatibility with 10/100Mb PRU_ICSS
- Each PRU_ICSSG contains 3x PRU RISC Cores per Slice (2x Slice per PRU_ICSSG): PRU General Use core (PRU), PRU Real-Time Unit core (PRU-RTU), PRU Transmit core (PRU-TX)
- Each PRU core supports: Instruction RAM with ECC, Broadside RAM Multiplier with optional accumulator (MAC), CRC16/32 hardware accelerator, Byte swap for Big/Little Endian conversion, SUM32 hardware accelerator for UDP checksum, Task Manager for preemption support
- Up to 2x Ethernet ports: RGMII (10/100/1000), MII (10/100)
- Three Data RAMs with ECC, 8 banks of 30 x 32-bit register scratchpad memory
- Interrupt controller and task manager
- 2 x 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
- 18x Sigma-Delta Filter Module (SDFM) interfaces
- Short circuit logic
- Over-current logic
- 6x Multi-protocol position encoder interfaces
- 1 x Enhanced Capture Module (ECAP)
- 16550-compatible UART
- Dedicated 192-MHz clock to support 12-Mbps PROFIBUS
- Security:
- Secure Boot supported
- Hardware-enforced Root-of-Trust (RoT)
- Support to switch RoT via backup key
- Support for takeover protection, IP protection, and anti-roll back protection
- Support for cryptographic acceleration
- Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
- DMA support
- Supports cryptographic cores: AES - 128/192/256-bit key sizes, 3DES - 56/112/168-bit key sizes, MD5, SHA1, SHA2 - 224/256/384/512-bit key sizes, DRBG with true random number generator, PKA (Public Key Accelerator) to Assist in RSA/ECC processing
- Debugging security: Secure software-controlled debug access, Security aware debugging
- Secure storage support
- On-the-Fly encryption (OTFE) support for OSPI in XIP mode
- Networking security support for data (Payload) encryption/authentication via packet-based hardware cryptographic engine
- DMSC-L co-processor for security and key management, with dedicated device level interconnect
- General connectivity peripherals:
- 6x Inter-Integrated Circuit (I2C) ports
- 9x configurable Universal Asynchronous Receive/ Transmit (UART) modules
- 1 x 12-bit Analog-to-Digital Converters (ADC): Configurable sample rate up to 4 MSPS, 8x multiplexed analog inputs
- 7x Multichannel Serial Peripheral Interfaces (SPI) controllers
- 3x General-Purpose I/O (GPIO) modules
- Industrial and control interfaces:
- 9x Enhanced Pulse-Width Modulator (EPWM) modules
- 3x Enhanced Capture (ECAP) modules
- 3x Enhanced Quadrature Encoder Pulse (EQEP) modules
- 2x Modular Controller Area Network (MCAN) modules with full CAN-FD support
- 2x Fast Serial Interface Transmitter (FSITX) cores
- 6x Fast Serial Interface Receiver (FSIRX) cores
- High-speed interfaces:
- 1 x Integrated Ethernet switch supporting up to 2 external ports (CPSW3G): Up to 2 Ethernet ports, RGMII (10/100/1000), RMII (10/100), IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP, Clause 45 MDIO PHY management, Energy efficient Ethernet (802.3rd)
- 1 x PCI-Express Gen2 controller (PCIE): Supports Gen2 Single Lane operation
- 1 x USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS): Port configurable as USB host, USB device, or USB Dual-Role device. USB device: High-speed (480 Mbps) and Full-speed (12 Mbps). USB host: SuperSpeed Gen 1 (5 Gbps), High-speed (480 Mbps), Full-speed (12 Mbps), and Low-speed (1.5 Mbps). Integrated USB VBUS detection
- 1 x Serializer/Deserializer (SERDES): One SerDes PHY lane to support either PCI-Express Gen2 or USB Super-Speed Gen1
- Media and data storage:
- 2x MultiMedia Card/Secure Digital (MMCSD) interfaces: One 8-bit for eMMC (MMCSD0), One 4-bit for SD/SDIO (MMCSD1). Integrated analog switch for voltage switching between 3.3V to 1.8V for high-speed card
C20345195 EasyEDA 라이브러리
컴플라이언스 & 수출 코드
| 타입 | 세부사항 |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 5A992C |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| 타입 | 세부사항 |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 5A992C |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| 타입 | 세부사항 |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |