LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Everspin Tech EMD3D256M08G1-150CBS1R product image
Images for reference only

Everspin Tech EMD3D256M08G1-150CBS1RRoHS

Manufacturer
MPN
EMD3D256M08G1-150CBS1R
LCSC Part #
C20342495
Packaging
-
Customer #
Key Attributes
Memory RoHS
Datasheetpdf iconEverspin Tech EMD3D256M08G1-150CBS1R
Out of Stock
Notify Me
Minimum: 1Multiple: 1Sales Unit: Piece
Add to BOM List
QtyUnit Price(Reference Only)Total Amount
1+$ 136.5994$ 136.60
200+$ 54.5049$ 10900.98
500+$ 52.6838$ 26341.90
1,000+$ 51.7832$ 51783.20
Standard Packaging2000/Full Reel
Better price for more quantity?
$

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory
ManufacturerEverspin Tech
Packaging-
FeaturesOn-chip DLL clock alignment function;Power-up/power-down/under-voltage data protection function

Introduction

AI Translation

EMD3D256M08/16B 256Mb DDR3 Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a non-volatile memory that delivers non-volatility and high endurance at DDR3 speeds. The device supports DDR3 operation at rates up to 1333MT/Sec/Pin. It is designed to be fully compliant with all DDR3 DRAM characteristics, including on-die termination (ODT) and internal ZQ calibration, while offering the advantages of data persistence and extremely high write cycle endurance. Using spin-torque MRAM technology, no cell refresh is required, which greatly simplifies system design and reduces overhead. All control and address inputs are synchronized to a pair of externally supplied differential clocks, with input latching occurring at the clock crossover points. I/O is synchronized to a pair of bidirectional strobe signals (DQS, DQS̄). The device employs a RAS̄/CAS̄ multiplexed scheme and operates at 1.5V.

Features

AI Translation
  • 256Mb ST-DDR3 Spin-Transfer Torque Magnetic RAM
  • Non-volatile 256Mb (32Mb x 8, 16Mb x 16) DDR3
  • Supports standard DDR3 SDRAM features
  • VDD = 1.5V ± 0.075V
  • Up to 667MHz fCK (1333MT/sec/pin)
  • Page size 512-bit (x8) or 1024-bit (x16)
  • On-die termination
  • On-chip DLL aligns DQ, DQS, DQS (overline) transitions to CK transitions
  • All address and control inputs latched on rising clock edge
  • Burst length 8, programmable burst truncation length 4
  • Standard 10x13mm 78-ball (x8) or 96-ball (x16) BGA package