ST M27C4002-10B1

The M27C4002 is a 4 Mbit EPROM available in both UV-erasable and one-time programmable (OTP) versions. It is ideally suited for microprocessor systems requiring large programs, organized as 262,144 words of 16 bits. The FDIP40W (window ceramic frit-seal package) features a transparent lid, allowing the user to expose the die to UV light to erase the bit pattern. New patterns can then be written to the device following the programming procedure. For applications requiring only a single programming with no need to erase content, the M27C4002 is offered in PDIP40, PLCC44, and TSOP40 (10×20 mm) packages. To meet environmental requirements, STMicroelectronics (ST) offers the M27C4002 in ECOPACK packages. ECOPACK packages are lead-free. The second-level interconnect class is marked on the package and inner box label, in compliance with JEDEC standard JESD97. Maximum ratings related to soldering conditions are also marked on the inner box label. The operating modes of the M27C4002 are listed in the operating modes table. Only a single supply is required in read mode. All inputs are TTL-compatible except for VPP and the 12V on A9 used for electronic signature. The M27C4002 has two control functions that must both be logically asserted simultaneously to obtain data at the outputs. Chip Enable (Ē) is the power control for device selection. Output Enable (Ḡ) is the output control for gating data to the output pins, independent of device selection. Assuming stable addresses, address access time (tAVQV) equals the delay from Ē to output (tELQV). Assuming Ē is low and the address has been stable for at least tAVQV - tGLQV, data is available at the outputs after a delay of tGLQV following the falling edge of Ḡ. The M27C4002 features a standby mode that reduces supply current from 50mA to 100μA. The M27C4002 is placed in standby mode by applying a CMOS high-level signal to the Ē input. In standby mode, the outputs are in a high-impedance state, independent of the Ḡ input. Since EPROMs are typically used in larger memory arrays, this product incorporates a two-line control function to accommodate multi-memory connection configurations. The two-line control function allows:

• Minimum possible memory power dissipation
• Complete assurance against output bus contention For most effective use of these two control lines, Ē should be decoded and used as the primary device selection function, while Ḡ should be connected in common to all devices in the array and tied to the read line of the system control bus. This ensures all deselected memory devices remain in low-power standby mode, and output pins are activated only when data is required from a specific device.

• Supply voltage for read operations: 5V ± 10%
• Access time: 45ns
• Low power consumption
• Operating current at 10MHz: 70mA
• Standby current: 100μA
• Programming voltage: 12.75V ± 0.25V
• Programming time: 100μs/word
• Electronic signature
• Manufacturer code: 20h
• Device code: 44h
• Available in ECOPACK packages
• FDIP40W (F)
• PDIP40 (B)
• PLCC44 (C)
• TSOP40 (N) 10×20mm