Infineon S25FL129P0XBHV310

The S25FL129P is a 3.0 Volt (2.7V to 3.6V), single-power-supply Flash memory device. The device is offered in two configurations: 256 uniform 64 KB sectors with the two (Top or Bottom) 64 KB sectors further split up into thirty-two 4 KB sub sectors, or 64 uniform 256 KB sectors. The S25FL129P device is backward compatible with the S25FL128P (uniform 256 KB sector) device. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3.0-volt VCC supply. device adds the following high-performance features using 5 new instru Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz Quad Output Read using SI, SO, W#/ACC and HOLD# pins as output pins at a clock rate of up to 80 MHz Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up to 80 MHz Quad I/O High Performance Read using SI, SO, W#/ACC and HOLD# pins as input and output pins at a clock rate of up

• Single power supply operation – Full voltage range: 2.7 to 3.6V read and write operations
• Memory architecture – Uniform 64 KB sectors – Top or bottom parameter block (Two 64-KB sectors broken down into sixteen 4-KB sub-sectors each) – Uniform 256 KB sectors (no 4-KB sub-sectors) – 256-byte page size – Backward compatible with the S25FL128P (uniform 256 KB sector) device
• Program – Page Program (up to 256 bytes) in 1.5 ms (typical) – Program operations are on a page by page basis – Accelerated programming mode via 9V W#/ACC pin – Quad Page Programming
• Erase – Bulk erase function – Sector erase (SE) command (D8h) for 64 KB and 256 KB sectors – Sub-sector erase (P4E) command (20h) for 4 KB sectors (for uniform 64-KB sector device only) – Sub-sector erase (P8E) command (40h) for 8 KB sectors (for uniform 64-KB sector device only)
• Cycling endurance – 100,000 cycles per sector typical
• Data retention – 20 years typical
• Device ID – JEDEC standard two-byte electronic signature – RES command one-byte electronic signature for backward compatibility
• One time programmable (OTP) area for permanent, secure identification; can be programmed and locked at the factory or by the customer
• CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices
• Process technology – Manufactured on 0.09 μm MirrorBit® process technology
• Package option – Industry Standard Pinouts – 16-pin SO package (300 mils) – 8-contact WSON package (6x8 mm) – 24-ball BGA (6x8 mm) package, 5x5 pin configuration – 24-ball BGA (6x8 mm) package, 6x4 pin configuration
• Speed – Normal READ (Serial): 40 MHz clock rate – FAST_READ (Serial): 104 MHz clock rate (maximum) – DUAL I/O FAST_READ: 80 MHz clock rate or 20 MB/s effective data rate – QUAD I/O FAST_READ: 80 MHz clock rate or 40 MB/s effective data rate
• Power saving standby mode – Standby Mode 80 μA (typical) – Deep Power-Down Mode 3 μA (typical)
• Memory protection – W#/ACC pin works in conjunction with Status Register Bits to protect specified memory areas – Status Register Block Protection bits (BP2, BP1, BP0) in status