RENESAS R9A07G084M04GBA#AC0

200/400 MHz, Arm Cortex - R52 on - chip FPU and NEON, 1.5 MB of on - chip SRAM, Ethernet MAC, EtherCAT, USB 2.0 high - speed, CAN/CANFD, various communications interfaces such as an xSPI and ΔΣ interface, and security functions

• On - chip 32 - bit Arm Cortex - R52 processor
  • High - speed realtime control with operating frequency of 200/400 MHz On - chip Single 32 - bit Arm Cortex - R52 (revision rlp2)
  • Tightly coupled memory (TCM) with ECC CPU0:138 KB/128 KB
  • Instruction cache/data cache with ECC CPU0:16 KB per cache High - speed interrupt
  • The FPU supports addition, subtraction, multiplication, division, multiply - and - accumulate, and square - root operations at single - precision and double - precision.
  • The NEON, Advanced SIMD, supports integer or single precision results.
  • Harvard architecture with 8 - stage pipeline Supports the memory protection unit (MPU)
  • Arm CoreSight architecture, includes support for debugging through JTAG and SWD interfaces.
• Low power consumption
  • Standby mode and module stop function
• On - chip SRAM
  • 1.5 MB of the on - chip SRAM with ECC 150/200 MHz
• Data transfer
  • DMAC:8 channels × 2 units
• Event link controller
  • Module operations can be started by event signals rather than by interrupt handlers Linked operation of modules is available even while the CPU is in the standby state.
  • Reset and power supply voltage control Four reset sources including a pin reset
• Clock functions
  • Clock functions - External clock/oscillator input frequency: 25 MHz - CPU clock frequency: 200/400 MHz or 150/300 MHz - System clock frequency: 200 MHz or 150 MHz - Low - speed on - chip oscillator (LOCO): 240 kHz
• Safety functions
  • Safety functions - Register write protection, input clock oscillation stop detection and CRC - Master Memory Protection Unit (MPU)
• Security functions (optional)
  • Boot mode with security through encryption JTAG authentication Cryptologic accelerator TRNG
• Various communications interfaces
  • Various communications interfaces - Ethernet - Ethernet CAT slave Controller: 3 ports - Ethernet switch: 3 ports - Ethernet MAC: 1 port - USB 2.0 high - speed host/functions: 1 channel - CAN/CANFD (compliant with ISO11898.1): 2 channels - SCI with 16 - byte transmission and reception FIFOs: 6 channels - I²C bus interface: 3 channel for transfer at up to 400 kbps - SPI: 4 channels - xSPI: 2 channels
• External host interfaces
  • Serial host interface (SHOSTIF) - Parallel host interface (PHOSTIF)
• External address space
  • Buses for high - speed data transfer at up to 100 MHz Support for up to 4 Gs areas 8 - or 16 - bit bus space is selectable per area
• Up to 35 extended - function timers
  • Up to 35 extended - function timers - 16 - bit × 8 + 32 - bit MTU3 (9 channels), 32 - bit GPT (18 channels): Input capture, output compare, PWM waveform output - 16 - bit CMT (6 channels), 32 - bit CMTW (2 channels)
• ΔΣ interface
  • Up to 6ΔΣ modulators are connectable externally.
• Trigonometric function unit
  • Trigonometric function unit - Simultaneous calculation of sine and cosine - Simultaneous calculation of arctangent and hypot_k
• 12 - bit A/D converter
  • 12 bits × 2 unit (4 channels for unit 0, 8 channels for unit 1)
  • Temperature sensor for measuring temperature within the chip
• General - purpose I/O ports
  • Input pull - up/pull - down - The locations of input/output functions for peripheral modules are selectable from among multiple pins.
• Operating temperature range
  • I₂ = - 40 to +125°C