Qorvo PAC5524QF

The PAC5524 is optimized for high-pin count and high-speed BLDC motor control. It integrates a 150MHz Arm Cortex-M4F 32-bit microcontroller core with Active-Semi’s proprietary and patentpending Multi-Mode Power Manager, Configurable Analog Front-End and Application Specific Power Drivers to form the most compact microcontroller-based power and motor control solution available.

The PAC5524 microcontroller features 128kB of embedded FLASH and 32kB of SRAM memory, a 2.5MSPS analog-to-digital converter (ADC) with programmable auto-sampling of up to 24 conversion sequences, 3.3V IO, flexible clock control system, PWM and generalpurpose timers and several serial communications interfaces.

The Multi-Mode Power Manager (MMPM) provides “all-in-one” efficient power management solution for multiple types of power sources. It features a configurable multi-mode switching supply controller capable of operating a buck or SEPIC converter and up to four linear regulated voltage supplies. The Application Specific Power Drivers (ASPD) are power drivers designed for half bridge, Hbridge, 3-phase, and general-purpose driving. The Configurable Analog Front End (CAFE) comprises differential programmable gain amplifiers, single-ended programmable gain amplifiers, comparators, digital-to-analog converters, and I/Os for programmable and interconnectible signal sampling, feedback amplification, and sensor monitoring of multiple analog input signals.

The PAC5524 is packaged in an 8×8mm, 64-lead QFN package with for compact battery-powered BLDC motor applications.

• Optional multi-mode switching supply controller configurable for DC/DC Buck or SEPIC topologies
• Direct DC supply up to 20V
• Integrated LDOs for MCU core, IO, analog with power and hibernate management
• Power and temperature monitor, warning and fault detection
• Low-power total hibernate mode, lQ = 18μA
• 3 Differential Programmable-gain Amplifiers
• 4 Single-ended Programmable-gain Amplifiers
• 2.5V ADC reference
• Programmable over-current shutdown
• Hibernate push-button wake-up
• Power supply monitoring via ADC
• Integrated level shifters and pre-drivers
• 3 Low-side and 3 High-Side gate drivers with 1.5A gate driving capacity
• Break-before-make (BBM) hardware dead-time enforcement to prevent shoot-through
• Configurable propagation delay and fault protection
• OC, UV protection
• 150MHz Arm Cortex-M4F MCU
• Hardware multiplier and divider
• Single-precision Floating Point Unit (FPU)
• Nested Vectored Interrupt Controller (NVIC) with 32 interrupts and 8 priority levels
• Clock-gating for low-power operation
• Embedded Trace Macrocell (ETM) for in-system debugging in real-time without breakpoints
• 128kB FLASH, 32kB SRAM with ECC
• 2 x 1kB INFO FLASH for manufacturing information
• 1 x 1kB INFO FLASH for user parameter storage and application configuration code
• 4-level user-configurable code protection
• 12-bit 2.5MSPS SAR ADC
• Dynamic Triggering and Sequence Engine (DTSE)
  • Up to 16 configurable sequences
  • Dedicated memory for conversion results
• 3.3V digital input/output or analog input for ADC
• Configurable weak pull-up or pull-down
• Configurable drive strength (6mA to 25mA minimum)
• Flexible peripheral MUX allowing each IO pin to select from up to 8 peripheral functions
• Flexible interrupt controller
• 300MHz PLL from internal 2% oscillator
• 20MHz ring oscillator
• Optional 20MHz external clock input
• Four 16-bit PWM timers with up to 8 CCR output units each
• 24-bit SysTick count-down timer
• Windowed Watch-dog Timer (WWDT)
• 24-bit Real-Time Clock (RTC) with calendar and alarm
• 2×24-bit General-purpose count-down timers with interrupt
• Hibernate wake-up timer for sleep modes from 0.125s to 8s
• 3x USART (UART or SPI)
• I2C master/slave
• SPI master/slave, up to 25MHz
• CAN 2.0B Controller
• SWD or JTAG serial debug interfaces
• Embedded Trace Macrocell (ETM)
• 8b/16b CRC Engine
• 96-bit Unique ID
• TA = -40 to 125°C
• QFN 8x8mm 64-pin package
  • Exposed pad for thermal management