Infineon CYWB0226ABMX-FDXIT

The Simultaneous Link to Independent Multimedia (SLIM) architecture allows three different interfaces (P-port, S-port and U-port) to connect to one another independently. With this architecture, connecting a device using Astoria to a PC through USB does not disturb any of the functions of the device. The device can still access mass storage at the same time the PC is synchronizing with the main processor. The SLIM architecture enables new usage models in which a PC can access a mass storage device independent of the main processor, or enumerate access to both the mass storage and the main processor at the same time. In a handset, this typically enables using the phone as a thumb drive, downloading media files to the phone while still having full functionality available on the phone, or using the same phone as a modem to connect the PC to the web. The 8051 microprocessor embedded in Astoria does basic transaction management for all the transactions between P-Port, S-Port, and U-Port. The 8051 does not reside in the data path; it manages the path. The data path is optimized for performance. The 8051 executes firmware that supports NAND, SD, SDIO, MMC+, and CE-ATA devices at the S-Port. For the NAND device, the 8051 firmware follows the smart media algorithm to support physical to logical management, four random bits ECC detection and correction support, wear leveling, and NAND Flash bad blocks handling. The West Bridge Astoria device includes configuration and status registers that are accessible as memory mapped registers through the processor interface. The configuration registers allow the system to specify certain behavior of Astoria. For example, it is able to mask certain status registers from raising an interrupt. The status registers convey various status, such as the addresses of buffers for read operations. Communication with the external processor is realized through a dedicated processor interface. This interface is configured to support different interface standards. This interface supports multiplexing and nonmultiplexing address or data bus in both synchronous and asynchronous pseudo CRAM-mapped, and nonmultiplexing address or data asynchronous SRAM-mapped memory accesses. The interface also can be configured to a pseudo NAND interface to support the processor’s NAND interface. In addition, this interface can be configured to support SPI slave. Asynchronous accesses can reach a bandwidth of up to 66.7 MBps. Synchronous accesses can be performed at 33 MHz across 16 bits for up to 66.7 MBps bandwidth. The memory address is decoded to access any of the multiple endpoint buffers inside Astoria. These endpoints serve as buffers for data between each pair of ports, for example, between the processor port and the USB port. The processor writes and reads into these buffers via the memory interface. Access to these buffers is controlled by either using a DMA protocol or using an interrupt to the main processor. These two modes are configurable by the external processor. As a DMA slave, Astoria generates a DMA request signal to signify to the main processor that a specific buffer is ready to be read from or written to. The external processor monitors this signal and polls Astoria for the specific buffers ready for read or write. It then performs the appropriate read or write operations on the buffer through the processor interface. This way, the external processor only deals with the buffers to access a multitude of storage devices connected to Astoria. In the Interrupt mode, Astoria communicates important buffer status changes to the external processor using an interrupt signal. The external processor then polls Astoria for the specific buffers ready for read or write, and it performs the appropriate read or write operations through the processor interface. In accordance with the USB 2.0 specification, Astoria can operate in Full Speed USB mode in addition to High Speed USB. The USB interface consists of the USB transceiver. The USB interface is accessible by both the P-Port and the S-Port. The Astoria USB interface supports programmable CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints. Astoria also has an integrated USB switch that allows interfacing to an external Full Speed USB PHY. The S-Port is configurable in six different interface modes, either simultaneously supporting an SD/SDIO/MMC+./CE-ATA port and a 8-bit SLC or MLC.

• N-Xpress NAND controller technology
• Interleave up to 16 NANDs with 8 chip enables (CE#) for x8 or x16 SLC (CYWB0224ABS) or MLC (CYWB0224ABM) NAND Flash devices
• 4-bit error correction coding
• Bad block management
• Static wear leveling
• Multimedia device support
• Up to 2 SD, SDIO, MMC, MMC+, and CE-ATA devices
• SLIM architecture, allowing simultaneous and independent data paths between the processor and USB, and between the USB and mass storage
• High speed USB at 480 Mbps
• USB 2.0 compliant
• Integrated USB switch
• Integrated USB 2.0 transceiver, smart serial interface engine
• 16 programmable endpoints
• Flexible processor interface, which supports multiplexing and nonmultiplexing address and data interface, SRAM interface, pseudo CRAM interface (Antioch interface), pseudo NAND Flash interface, SPI (slave mode) interface, DMA slave support
• Low power modes
• Small footprint, 6x6mm VFBGA
• Supports I2C boot and processor boot
• Selectable clock input frequencies: 19.2 MHz, 24 MHz, 26 MHz, and 48 MHz

• Cellular Phones
• Portable Media Players
• Personal Digital Assistants
• Portable Navigation Devices
• Digital Cameras
• POS Terminals
• Portable Video Recorders
• Data Cards and Wireless Dongles