AP Memory APS1604M-3SQR-SN

This Pseudo-SRAM device features a high speed, low pin count interface. It has 4 I/O pins and operates in SPI(serial peripheral interface) or QP (quad peripheral interface) mode with frequencies up to 133 MHz. The data input (A/DQ) to the memory relies on clock (CLK) to latch all instructions, addresses and data. It is most suitable for low-power and low cost portable applications. It incorporates a seamless self-managed refresh mechanism. Hence it does not require the support of DRAM refresh from system host. The self-refresh feature is a special design to maximize performance of memory read operation.

• Output Driver LVCMOS with programmable drive strengths of 50, 100 and 200Ω
• Dedicated Wrapped Burst read and write commands
• Linear 512 Length Burst is supported up to 84MHz and can cross page boundary as long as tCEM is met
• Register Configurable Wrap Lengths of 16, 32, 64 and 512
• Burst Length Toggle Command to switch between configurable wrap length and 32 bytes wrap
• Software Reset