Insignis Technology Corporation NDQ48PFQ-8NET TR

DDR4 SDRAM is a high-speed dynamic random access memory with an internal organization of 16 banks (4 bank groups, 4 banks per group). DDR4 SDRAM employs an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is coupled with an interface designed to transfer two data words per clock cycle at the I/O pins. A single DDR4 SDRAM read or write operation consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit wide, half-clock-cycle data transfers at the I/O pins.

Read and write accesses to the DDR4 SDRAM are burst-oriented, starting at a selected location and continuing for a burst length of 8 or a "truncated" burst length of 4 in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank group and row to be activated (BG0 selects the bank group; BA0–BA1 select the bank; A0–A14 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst operation, to determine whether an Auto Precharge command is to be issued (via A10), and to "on-the-fly" select BC4 or BL8 mode (via A12) when enabled by the mode register.

Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information on device reset and initialization, register definitions, command descriptions, and device operation.

• JEDEC compliant
• Fast clock rate: 1200/1333MHz
• Power supply:
  • VDD and VDDQ = +1.2V ± 0.06V
  • VPP = +2.5V - 0.125V / +0.25V
• Operating temperature range:
  • Extended Test (ET): TC = 0 ~ 95°C
  • Industrial Temperature (IT): TC = -40 ~ 95°C
  • Automotive Temperature (AT): TC = -40 ~ 105°C
• Supports JEDEC clock jitter specification
• Differential bidirectional data strobe, DQS and DQS#
• Differential clock, CK and CK#
• 16 internal banks: 4 bank groups, 4 banks per group
• Per-bank-group I/O gating architecture
• 8n-bit prefetch architecture
• Precharge and active power down
• Auto refresh and self refresh
• Low Power Auto Self-Refresh (LPASR)
• Self-refresh abort
• Fine granularity refresh
• Write leveling
• DQ training via MPR
• Programmable preamble supporting 1tCK and 2tCK modes
• Command/Address (CA) parity
• Data bus write Cyclic Redundancy Check (CRC)
• Internal VREFDQ training
• Read preamble training
• Gear-down mode
• Per-DRAM addressability (P)
• Output driver impedance control
• Dynamic On-Die Termination (ODT)
• Input data mask (DM) and data bus inversion (DBI)
• ZQ calibration
• Command/Address Latency (CAL)
• Maximum Power Saving Mode (MPSM)
• Asynchronous reset
• DLL enable/disable
• Burst length (BL8/BC4/BC4 or on-the-fly select 8)
• Burst type: sequential/interleave
• CAS Latency (CL)
• CAS Write Latency (CWL)
• Additive Latency (AL): 0, CL - 1, CL - 2
• Average refresh period:
  • 8192 cycles/64ms (7.8us at -40°C ≤ TC ≤ +85°C)
  • 8192 cycles/32ms (3.9us at +85°C ≤ Tc ≤ +95°C)
  • 8192 cycles/16ms (1.95us at +95°C ≤ TC ≤ +105°C)
• Data interface: Pseudo Open Drain (POD)
• RoHS compliant
• Hard Post Package Repair (hPPR)
• Soft Post Package Repair (sPPR)
• 78-ball 7.5×10.6×1.2mm FBGA package
• Lead-free and halogen-free